Implement Reset in Simulink

Hallo

We have an altrea FPGA, we are generating the design using simulink and then use the hdl coder to generate the vhdl code. We use the generated vhdl project file in quartus to download the program in our fpga. we get an warning from altera which is the following

Rule R102: External reset signals should be synchronized using two cascaded registers

we are currently using an Asynchronous reset, because synchronous reset uses a lot of resources, which leads to speed issue.

how can we solve this problem from simulink?

Answer 1

[Kiran Kintali]

These page describes how to generate code with synchronous or asynchronous reset.

web(fullfile(docroot, 'hdlcoder/ug/reset-and-clock-enable-settings.html'))

Asynchronous

Use asynchronous reset logic. This reset logic samples the reset independent of the clock signal.

The following process block, generated by a Unit Delay block, illustrates the use of asynchronous resets. When the reset signal is asserted, the process block performs a reset, without checking for a clock event.

Unit_Delay1_process : PROCESS (clk, reset)

BEGIN

IF reset = '1' THEN

Unit_Delay1_out1 <= (OTHERS => '0');

ELSIF clk'event AND clk = '1' THEN

IF clk_enable = '1' THEN

Unit_Delay1_out1 <= signed(x_in);

END IF;

END IF;

END PROCESS Unit_Delay1_process;

web(fullfile(docroot, 'hdlcoder/ug/guidelines-for-clock-and-reset-signals.html'))

web(fullfile(docroot, 'hdlcoder/ug/check-for-global-reset-setting-for-xilinx-and-altera-devices.html'))