HDL Coder Filter - Latency and Clock rate

Hi,

When Matlab generates the HDL code for my FIR filter design it shows:

### Clock rate is 201 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: Hlp
### HDL latency is 3 samples

I have two doubts about it. First, is the HDL latency of 3 samples the group delay of the filter?

Second, "clock rate is 201 times the input sample rate" means that my frequency should be exactly that number or it can be greater? If so, does it have to be an integer multiple of my clock rate?

Thanks.

Answer 1

[Bharath Venkataraman]

The latency of 3 samples is not the group delay of the filter. It specified the number of pipeline delays in the data processing chain.

The ratio of sample rate to clock rate is reported as 201. There is an internal timing controller generating the local clock enable which enforces this rate, so you will need to maintain this rate.

[Lucas Santos]

How does this internal timing controller affect the timing analysis of my synthesis tool? I am not being able to pass through timing analysis of filters implemented on HDL coder.

Answer 2

[Bharath Venkataraman]

I assume that you are sharing resources in the filter implementation leading to the 201x clock requirement.

If your design synthesizes to 201 MHz, you will only be able to send inputs in at 1 Msps to the filter. If that constraint is not acceptable, I suggest sharing less to make the 201x factor go down.