Assertion failed: b:\matlab\src\cgir_hdl\pir_transforms\datarateanalyzer.cpp:582:PirUtils::floatEqual(data.getRate(), outputSig->getRate())
4 Ansichten (letzte 30 Tage)
Ältere Kommentare anzeigen
Mohammed Shameem Hussain
am 16 Jul. 2017
Beantwortet: Kiran Kintali
am 19 Jul. 2017
I am trying to convert my HDL coder project to verilog files via HDL coder workflow.
This error HDL code generation report.
Error Assertion failed: b:\matlab\src\cgir_hdl\pir_transforms\datarateanalyzer.cpp:582:PirUtils::floatEqual(data.getRate(), outputSig->getRate())
Failed Assertion failed: b:\matlab\src\cgir_hdl\pir_transforms\datarateanalyzer.cpp:582:PirUtils::floatEqual(data.getRate(), outputSig->getRate())
Assertion failed:
b:\matlab\src\cgir_hdl\pir_transforms\datarateanalyzer.cpp:582:PirUtils::floatEqual(data.getRate(), outputSig->getRate())
Error in slhdlcoder.HDLCoder/makehdl
Error in downstream.DownstreamIntegrationDriver/runGenerateRTLCodeAndTestbench
Error in runGenerateRTLCodeAndTestbench
Error in Simulink.ModelAdvisor/executeCheckCallbackFct
Error in Simulink.ModelAdvisor/run
Error in Simulink.ModelAdvisor/runCheck
Error in ModelAdvisor.Node/runTaskAdvisor
Error in ModelAdvisor.Node/runToFail
Error in ModelAdvisor.Node.runtofailure
Failed Generated HDL code.
Please suggest me how to proceed. I am using Matlab 2017a.
2 Kommentare
Walter Roberson
am 16 Jul. 2017
This seems to be indicating that the data rate has been detected as being different from the output signal rate.
Akzeptierte Antwort
Kiran Kintali
am 19 Jul. 2017
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/177500/image.jpeg)
Hi, we have analyzed this issue and it looks like some of your blocks are configured with different rate inputs as you can see in the picture. This is not supported by HDLCoder.
We are investigating why you were seeing the cryptic error instead of valid error message pointing you to the incorrectly configured product block. We will fix this buggy behavior in our 17b release.
For now, can you make sure the rates are consistent in your model?
we are working with Simulink team to report this error as soon as possible (ctrl-D) during rate propagation and also update HDLCoder conformance checker to report a valid message pointing to the offending block instead of the cryptic internal error.
Hope this helps.
Thanks
0 Kommentare
Weitere Antworten (1)
Kiran Kintali
am 17 Jul. 2017
can you please send me reproduction steps with a model? my team will provide a workaround for 17a. thanks.
3 Kommentare
Siehe auch
Produkte
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!