HDL coder simulation for video processing takes very long time. Is there way to do it faster ?
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Mohammed Shameem Hussain
am 25 Mai 2017
Kommentiert: Mohammed Shameem Hussain
am 30 Mai 2017
I have discrete-time settings with fixed step of 1. The frame size of video input 480 x 640.
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Bharath Venkataraman
am 26 Mai 2017
This is because of the pixel level processing. 480x640 translates to over 300K pixels per frame (not including blanking). Are you using Vision HDL Toolbox for this simulation with Frame To Pixels and Pixels To Frame blocks? If so, you have two options: 1. In Simulink, make sure that the model is in Accelerator/Rapid Accelerator mode. 2. Use a smaller image (say 60x80) to prove out your algorithm and run it on the larger frame size when you get to FPGA-in-the-Loop.
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