Unable to create project in xilinx vivado 2015.2 from simulink using hdl workflow adviser,Getting error [12-172],how can get pass this?
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Hi,
I am trying to run HDL work flow adviser for the standard LED blink example from MATLAB. I am new to this style of programming FPGA, can someone advice me what to do or where I can find a solution. This is the following error:
Failed
INFO: [Ipptcl 7-578] No Compatible Board Interface found.Board Tab not created
VHDL Output written to : C:/MATLAB Saved files/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/hdl/system_top.vhd
VHDL Output written to : C:/MATLAB Saved files/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/hdl/system_top_wrapper.vhd
Wrote : <C:/MATLAB Saved files/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/system_top.bd>
make_wrapper: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 390.328 ; gain = 123.043
# regsub -all "system_top.vhd" [get_files system_top.vhd] "system_top_wrapper.vhd" TOPFILEPATH
# add_files -norecurse $TOPFILEPATH
ERROR: [Vivado 12-172] File or Directory 'Saved' does not exist
INFO: [Common 17-206] Exiting Vivado at Thu Mar 30 11:54:46 2017...
Elapsed time is 11.1759 seconds.
3 Kommentare
Walter Roberson
am 30 Mär. 2017
Sorry, I do not have any experience with that.
You might need to contact Mathworks Support
Antworten (1)
Kiran Kintali
am 15 Nov. 2021
Generate Custom HDL IP Core for Blinking LED on FPGA Board
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