Why am I getting inconsistent data from my HDL Coder implementation?

I developed an OFDM modulator using Matlab then I converted it into VHDL using HDL Coder tool. The problem is that HDL Coder generate a lot of synthesis warnings. I think that may be the problem.

Does anyone have any suggestions or had had the same problem?

I am using Matlab 2016b and ISE Design Suite 14.7 (The .vhd files generated by HDL Coder are sythesized in ISE)

Answer 1

[Kiran Kintali]

Please reach out to [e-mail] with reproduction steps.