FFT HDL Optimized input vector size of only 64

I noticed in the latest FFT HDL Optimized blocks, which implements a faster pipelined Radix 2^2 FFT algorithm and essentially replaces the HDL Streaming FFT block, that the maximum vector size is only 2^6 = 64. First of all its already one of the best updated changes ever, given before you had to implement a cumbersome streaming serial mechanism using additional blocks and tricks and the radix was different. It was basically a nightmare and the new blocks are better as it saves you time in preparing your input, however, the streaming blocks did have it benefits in that it allowed you to input a larger vector to stream as you see fit. The new FFT and IFTF blocks are great in that they allow for vector inputs int eh first place - a real luxury, but the problem is that 64 is still quite small (for some industries). Are there any plans in the next releases to increase this please. See table for DataIn under

http://uk.mathworks.com/help/dsp/ref/ffthdloptimized.html

In the meantime, how easy would it be (in order to make sure you get the cycles correct and timing) to make a cascaded version of the blocks if you need an input size vector of length 128. In other words how would one combine two FFT blocks. Can you split your vector before input and combine them after output to mimic a 128 size vector input. (Note I'm talking about the luxury of having the input as a vector, I'm not talking about FFT length here, that setting is fine)

Thanks

Answer 1

[Alireza]

It is possible to build N-point FFT using two N/2 point FFT. But it requires extra steps and it is not straight forward. For example for 1024 point FFT with 128 inputs, you use two 512 point FFT, each of them with 64 inputs. You need to split the inputs to even and odd samples. Then you need to combine the outputs of the FFTs. The even samples is basically the sum of two FFTs. But for the odd sample you need to run circular convolution. This step requires a lot of hardware.

I would like to understand your use case. Remember that with 64 inputs and running at 250MZ (on Xilinx Virtex 6), the throughput will be 16 Giga sample per second. Does your application require higher throughput?

Note that increasing the input vector size, make it harder for FPGA to route the signals. For some of the devices you may not be able to route the signals, and for other devices it will affect the maximum processing clock rate.

[DN]

Hi Alireza,

Any update yet in the new releases ahead, to increase the input vector size ?

Many Thanks

[Bharath Venkataraman]

Hi, would you be able to reach us through our support?

Thanks, Bharath