I want to covert MATLAB code to VHDL code using HDL coder. But I am getting following error. I have changed values many times but even also I am getting the same error .

### Begin TestBench generation.
Error using divide (line 169)
Division by zero detected.
Early termination due to division by zero.

Error in Float2FixedConverter>runTestBenchToLogDataNew/withScopeProtection/runSimWithTBEvalSimFcn at 567
Error in Float2FixedConverter>runTestBenchToLogDataNew at 495
Error in HDLCoderTB>computeData at 399
Error in HDLCoderTB>generateTB at 460
Error in Manager>wfa_runSimulation at 76

Answer 1

[Tim McBrayer]

If you have a data value that isn't originally zero, but becomes zero when quantized to fixed point, you could get this message. If you have a persistent variable feeding the divide, and the persistent value has an initial value of zero, that could be another possible cause.

Perhaps something like this might work:

 if b ~= 0
   c = a/b;
 else
   c = <max value for c's data type>;
 end

The larger issue is that you have some source code that is resulting in a division. In general, division with an arbitrary denominator is not supported for HDL Synthesis. Even if your tool can synthesize it, it will take a lot of FPGA real estate.

[Maximilian Sgodda]

Hi Tim,

I have a similiar issue. I want to implement a persistent variable that will be divided by a constant value. This constant value can be adjusted every time the script is running.

Later in the FPGA this "real" division should be implemented, since many FPGA have these Multipliers on board and can generate a division in fixed point.

How can I do this?

[Kiran Kintali]

What you describe should be possible. Please share a sample design dut.m and dut_testbech.m.