HDL Coder: Pipelined multipliers in logic

I want to implement a 8x8 bits multiplier via Simulink with LUTs (without DSP blocks). To optimize speed I wanted to introduce pipelines. My issue is that none of the settings I set for InputPipeline or OutputPipeline parameters improve timing.

I'm using Vivado Synthesis Tool for Zynq-7000 and R2015a. I disabled DistributedPipeling option and DSPstyle.

Here are the post-route timings I can achieve with some different settings: - No pipelining: 6.610ns - 7 output registers: 7.561ns - 7 input registers: 7.736ns

When I investigated the synthesized design, I figured out that in the synthesized design the multiplier is not pipelined at all, registers are only put at input or output of the multiplier.

How I can solve this problem and realize a fully pipelined multiplier in logic via Simulink ? Do I have to set some timing constraints to do so ?

Thank you for your help.

Answer 1

[Girish Venkataramani]

Hello,

What is the size of your multiplier (in terms of bit-width)? In R2015a, HDL Coder introduced an option to partition multipliers. If your multiplier is really wide bitwidth, then you can use this option by opening the configuration parameters dialog, go to 'HDL Code Generation -> Global Settings' and click on the 'Optimizations' tab. Here you will see a multiplier partitioning threshold. This is the input bitwidth of the multipliers - if you set this option, the multipliers in HDL will split in to smaller multiply-shift-add operations so that the input bitwidth doesn't exceed the threshold setting.

By default, this is at 'inf', so no partitioning happens by default. If you set this value, to say 18 or 8, and then turn on distributed pipelining, you will see that your multiplier gets pipelined.

Other things to check - see that you are using synchronous reset mode (again an option in the configuration parameters dialog).

Girish

[Thibault Gadeyne]

My multiplier is a 8x8. I originally thought the synthesis tool (i.e. Vivado) could handle the register balancing. Your solution is interesting and have good results on my multiplier example.

Why do I have to set synchronous reset mode ?

Thibault

[Girish Venkataramani]

I guess you don't need synchronous mode if you are mapping to LUTs and not DSPs. For mapping to DSPs, Vivado requires synchronous reset registers. So, if this solutions works for you (using multiplier partitioning), you're all set.