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Grid Connected VSI, PI controller output waveform never settles.

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I am designing and simulating a Virtual Synchronous machine which simulates an inertial response of a Synch. Gen.. I have designed the current loop such that the inverter follows the reference P & Q that I input to the system.
The issue I am facing is the PI controller I am using to make Id and Iq follow Id ref and Iq ref is working (i.e it follows the ref whenever we change it) but the oscillations never die out no matter how high Kp or Ki is, thus there is always an Ess no matter how small, the waveform never settles. I need help designing the controller such that the waveform settles.
In the image the red line is the reference signal and the blue is what the controller and current loop controls.

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Shivam Gothi
Shivam Gothi vor etwa 4 Stunden
Based on my understanding, it seems that the issue you're encountering is that the ("Id") and ("Iq") are not following their reference values.
After reviewing the model you provided, I have reached the following conclusions:
  • The voltage source inverter model appears to be good.
  • The controllers are well designed.
  • It seems the issue arises due to the use of “Goto” and “From” tags, which may be causing the signal to not properly transmit between blocks.
To address this, I have modified the sub-systems so that their “Goto” tag is positioned outside the block, as illustrated in the figure below. I have also shared the updated Simulink file with you (NOTE: I have saved the model in different simulink version. download the one according to the version you are using.).
Validating the Controller:
CASE-1: Change "Iqref" , keeping "Idref" = 0.
I applied a step increment to “Iqref” at various time intervals while maintaining “Idref = 0.” The results, shown below, indicate that the reference is being tracked accurately. ]
CASE 2: Change "Idref" by keeping "Iqref" = 10
Now, I set “Iqref = 10A” and incremented “Idref” in steps at different intervals. The results, also displayed below, confirm that the reference is tracked perfectly.
Further Steps:
You can now generate any “Idref” or “Iqref” by solving the Virtual Synchronous Machine model. The inverter's actual currents should track these references accurately.
I hope this information proves helpful !
NOTE: I have saved the model in different simulink version. download the one according to version you are using.
  3 Kommentare
Maaz Samir
Maaz Samir vor 34 Minuten
Also I tried recreating your model in my original model with all goto and from tags outside but could not recreate the results. So i copied your blocks into my models adn comment/uncomment individual block to find the faulty ones. I found that my current loop and iabc to idq were were as yours but if i use my PLL I am getting the following output eventhough our circuits and aprameters are exactly the same:
If I comment out my Pll and use yours I get the output u posted. Similiar issue is happening if I use my mdq to mabc which doesnt even run giving an inf error while using yours give me the correct output. Did u make any changes in these blocks that I cant see ?
Here is the simulink file I used to compare between yours and my blokcs.
Shivam Gothi
Shivam Gothi vor 25 Minuten
Glad to hear that the model is working as per your expectation.
Reason for small ripples:
From the waveform attached by you, It seems that the frequency of those ripples roughly corresponds to the line frequency, i.e 50Hz.
As per my understanding, in order to perfectly track the slow varying or DC reference voltages (with completely zero steady state error), we need to achieve infinite loop gain for low frequencies. But practically, it is not possible. Therefore, we may reach upto very high loop gain, but not infinite. This might be the cause behind the small oscillations.
How do I come to know about the "goto" tags ?
After exhausting all the possible solutions for troubleshooting, I asked myselves: "Are the "goto" tags inside the subsystem, visible to other sub-systems?"
After that, I tried on one of the signal. That is, I put the "goto" tag of one of the signals outside the subsystem. To my surprise, the results obtained were quite different from that obtained before. From this, I came to know that this might be causing the issue.

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