Loop based error while performing HDL conversion using HDL workflow

I am trying to find specific rows and columns of an image for image processing based project.I am trying find all the rows/columns which are row of 1.I am able to code it in MATLAB and get the right results but when I try to convert it into HDL format,I am facing this issue all the time and I am unable to proceed further.Although I am able to do it once for a specific row but not in a loop to check for all rows.

The error I am getting is:

My MATLAB code:

%Sample Test bench
x=[1,0,0,1,0;0,0,0,0,1;1,1,1,1,1;0,0,0,0,0;1,1,1,1,1];
[Row]=rowseg1(x);

%Design function
function [x]=rowseg1(image)
[m,~]=size(image);
u=1;
a=repelem(u,m);
x=zeros(1,m);
k=image(3,:);
for i=1:m
    if(image(i,:)==a)
        x(i)=i;
    else
        x(i)=0;
    end
end
end

[Walter Roberson]

Looks like a duplicate of https://www.mathworks.com/matlabcentral/answers/2086613-how-to-find-indices-of-array-in-hdl-coder?s_tid=srchtitle

[Kiran Kintali]

This is how you would make the above snippet generate synthesizable code. Notice that you need to run float2fixed conversation if you do not wish to have floating point relational operator in the synthesized hardware. For guidance related to really large image matrices as inputs see the other thread below on this page.

Testbench

x=[1,0,0,1,0;0,0,0,0,1;1,1,1,1,1;0,0,0,0,0;1,1,1,1,1];
[Row]=rowseg1(x);

DUT

%Design function
function [x]=rowseg1(image)
[m,~]=size(image);
u=1;
a=repelem(u,m);
x=zeros(1,m);
k=image(3,:);
for i=1:m
    if isequal(image(i,:), a)
        x(i)=i;
    else
        x(i)=0;
    end
end
end

Runme

cfg = coder.config('hdl');
cfg.TestBenchName = 'rowseg1_tb';
cfg.DesignFunctionName = 'rowseg1';
cfg.FloatingPointLibrary = 'NativeFloatingPoint';
cfg.AggressiveDataflowConversion = true;
codegen -config cfg

Answer 1

[Kiran Kintali]

Your MATLAB Coding style is incompatible with MATLAB to HDL workflow. Here are few general pointers while we respond to your specific question. To make the code compatible you have two choices...

• Option #1: Author the code as sample in and sample out format...

% for sample in and sample out code style follow the example below. 
% you can see how the image is serialized in the testbench and the 
% serialized image samples are passed into the DUT
>> mlhdlc_demo_setup('heq')

• Option #2: Author the code with frames and use automatic frame to sample conversion workflow...

% for frame in and frame out code style follow the example below
% you can see how hdl.npufun and hdl.iteratorfun functions are used to
% iterate on the input frame passed into the DUT
>> mlhdlc_demo_setup('fog')

You can see general HDL Coder compatible MATLAB coding style patterns here

https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-and-examples

[Siddarth S]

Sure.I'll look into it.

[Siddarth S]

Which method is better to get the output of the function as an array?I plan on using this in an another main code for which the output needs to be an array

[Kiran Kintali]

This 5min video shows the differences betweens the two strategies.

How to Deploy Frame-Based Models to FPGA/ASIC Using HDL Coder: https://www.youtube.com/watch?v=r3uLsF4TAkY

At a high level...

Option1 gives you highest level of control in terms of FPGA modeling. you would need to do scheduling of the data using valid/ready style interfaces, marshall the data into and out of the DUT in addition to the kernel of operation.

Option2 is the new and advanced HDL Coder workflow where algorithm stays at math level with matrix inputs and matrix outputs and HDL Coder takes care of all the scheduling when generating a sample based FPGA/ASIC code.

Here is an interesting example to

Compute Image Characteristics with a Frame-Based Model for HDL Code Generation

https://www.mathworks.com/help/hdlcoder/ug/compute-image-characteristics-with-frame-based-model-for-hdl-code-generation.html

[Siddarth S]

So based on this and some other research,I tried using iteratorfun since it keeps input at a matrix level which will better for this problem.But when try it,I am getting one error which I actually don't understand.

Error:

%Error calling 'test/rowseg'. This call-site passes more inputs to this function than it can accept.
%The error line in the function
outputData = iterFun(I(ii, jj), outputData, idx, varargin{:});

My code:

function y  = test(I)
%#codegen
[m,n]=size(I);
y=zeros(1,m);
for i=1:m
    out=0;
    out=hdl.iteratorfun(@rowseg,I,i,out);
    y(i)=out;
end
end

function x=rowseg(I,i)
[m,n]=size(I);
u=1;
a=repelem(u,m);
x=0;
if(I(i,:)==a)
    x=i;
end
end

[Kiran Kintali]

You are on the right path if you choose frame2sample path (where your DUT receives whole image as input).

However, you need to have a test.m that looks like...

% read an image...
I = imread(<file>);
[height, width] = size(imgOrig);
for height
     for width
         I_out = dut(I)
     end
end

and a dut.m that looks like this...

function I_out = dut(I)
... body that uses I and iterates on it using hdl.npufun and hdl.iteratorfun.
end

You need a runme.m file that looks like this... (see attached fog rectification example with a runme file)

% Runme file for fog rectification example design

% Provide Design Name and Testbench file.
designName = 'mlhdlc_fog_rectification';
designTB = 'mlhdlc_fog_rectification_tb';

% Create HDL config.
cfg = coder.config('hdl');
cfg.TestBenchName = designTB;

% Enable Frame to Sample Conversion
cfg.AggressiveDataflowConversion = true;
cfg.FrameToSampleConversion = true;

cfg.SynthesisTool = 'Xilinx Vivado';
cfg.SynthesizeGeneratedCode = true; % turn this if off if you just want RTL

cfg.SynthesisToolChipFamily = 'Artix7';
cfg.SynthesisToolDeviceName = 'xa7a100t';
cfg.SynthesisToolPackageName = 'csg324';
cfg.SynthesisToolSpeedValue = '-1I';

% Create inputs to provide code generation arguments
I = imread('inputFogRectification.png');
R = I(:,:,1);
G = I(:,:,2);
B = I(:,:,3);

% Call codegen with float2fixed and hdl config objects.
codegen('-config', 'cfg', designName, '-launchreport', '-args', {R,G,B});