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Resources utilization for generated HDL code

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Alex Alex
Alex Alex am 3 Mär. 2024
Kommentiert: Alex Alex am 5 Mär. 2024
I want to get resources utilization for generated HDL code (amount of LUTs, DSP blocks, FFs). Where can I find this information?
I have enabled optimization reports generation.
In code generation report target code generation tab is empty. It only contains following text: "This section is used for reporting the status of target-specific code generation". However, code has been already generated targeting specific device.

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Kiran Kintali
Kiran Kintali am 4 Mär. 2024
Bearbeitet: Kiran Kintali am 4 Mär. 2024
Please find the attached slides that show how to generate the FPGA Synthesis report from a Simulink model using HDL Coder.
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Kiran Kintali
Kiran Kintali am 5 Mär. 2024
Bearbeitet: Kiran Kintali am 5 Mär. 2024
IPcore generation step when executed only generates HDL code for the DUT, and the HDL IP core wrapper and packages the IP core files for use with the FPGA synthesis tools (Vivado, Quartus etc.,). HDL Coder does not run synthesis process in this step. Only the build bitstream type tasks runs synthesis+P/R+generate bitstream.
For IP core related workflow, your best options are to either run all steps up to the bitstream generation in the HDLWA an example shown here (https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-zynq-ultrascale-mpsoc-devices.html). You can perform these steps with Altera FPGA/SoCs as well.
Or as you mentioned you can import the IP core generated by HDL Coder from MATLAB and Simulink into your synthesis tool environment and run synthesis in Vivado / Quartus Pro to get the reports.
For early exploration you can also choose Generic ASIC/FPGA workflow, set Target Frequency, choose chip settings and synthesis tools and you will see synthesis steps in the workflow that generate reports. This workflow does not generate IP core. Once satisfied with the resource report you can switch to IP core based workflows.
Hope this is helpful.
Alex Alex
Alex Alex am 5 Mär. 2024
Thank you very much!

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Kiran Kintali
Kiran Kintali am 4 Mär. 2024
This is an estimation report from HDL Coder.
>> makehdl('sfir_fixed/symmetric_fir')
### Working on the model sfir_fixed
### Generating HDL for sfir_fixed/symmetric_fir
### Using the config set for model sfir_fixed for HDL code generation parameters.
### Searching for referenced models in model 'sfir_fixed'.
### Running HDL checks on the model 'sfir_fixed'.
### Begin compilation of the model 'sfir_fixed'...
### Working on the model 'sfir_fixed'...
### Working on... GenerateModel
### Begin model generation 'gm_sfir_fixed'...
### Copying DUT to the generated model....
### Model generation complete.
### Generated model saved at hdlsrc\sfir_fixed\gm_sfir_fixed.slx
### Begin VHDL Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as hdlsrc\sfir_fixed\symmetric_fir.vhd.
### Code Generation for 'sfir_fixed' completed.
### Generating HTML files for code generation report at sfir_fixed_codegen_rpt.html <==== Report Link
### Creating HDL Code Generation Check Report symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.
>>
Reports and Scripts
Traceability, optimization, and resource reports; standards compliance, synthesis scripts
The above report is an estimate of the algorithmic resources. To see the synthesis results (amount of LUTs, DSP blocks, FFs), you need to run upto synthesis in the workflow advisor with a specific target and frequency selections. You will see a summary of the resulting actual resources and timing in the log window.
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Alex Alex
Alex Alex am 4 Mär. 2024
Bearbeitet: Alex Alex am 4 Mär. 2024
I can not see synthesis results (amount of LUTs, DSP blocks, FFs) when using target workflow "IP Core Generation"

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