Results in FPGA-in-loop is different from Vivado simulation and how to debug

Hi there,

I'm newbee for FIL. Now I'm test some simple designs, like an adder.

The adder code is very simple and works well in Vivado simulation.

module adder (

a, b, c, clk, rst_n

);

input [15:0] a;

input [15:0] b;

input clk;

input rst_n;

output reg [15:0] c;

always @(posedge clk or negedge rst_n) begin

if (rst_n == 0) begin

c <= 0;

end

else begin

c <= a + b;

end

end

endmodule

After following the instructions of FIL wizard, the adder block cannot work as the supposed result "2". The result is always 0.

Normally the reason could be the clock is not working or reset keeps low (negative active in this case). But I don't know how to debug this in simulink.

And I think the inputs of FIL blocks should be discrete so I used zero-order-holder. But how to set an appropriate sample time for this? Is this related to the FIL block clock frequency?

Any thoughts would be appreciated!

Answer 1

[YP]

Did you set Reset asserted level to 'Active-low'?