How to add TCL script to HDL Coder IP Core generation

I use HDL Coder IP Core flow and I need to add a TCL script that I have to open Vivado, add the new IP core to the existing project and implement with it.

I tried "add additional sources" option in HDL Coder to point to my TCL script there. The TCL script was never executed.

Of course I can run the script manually after IP core is generated, but I want to have a pushbutton solution, such that I only start IP Core generation and everything else would work automatically.

One possible way would be to do everything (including IP core generation) in a TCL script, but I don't know how to make HDL coder to generate IP core in a TCL script.

Any suggestions?

Thank you, alex

Answer 1

[Wang Chen]

Hi Alex,

To clarify, "add additional sources" option (in HDL Workflow Advisor "Generate RTL code and IP core" step) is intended to include additional source files into the generated IP core. It will not execute the supplied Tcl script.

If you want to "I have to open Vivado, add the new IP core to the existing project and implement with it.", have you tried to create a custom reference design in IP core generation workflow? The steps to select a reference design (existing project), and run build tasks are exactly doing what you described. After you create a custom reference design, there are also callback functions you could use to execute your customized Tcl script.

Example of the IP core generation workflow with reference deisgn/bitstream build tasks; https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-zynq-ultrascale-mpsoc-devices.html

Document/Examples of creating a custom reference design to include your existing project into the workflow:

https://www.mathworks.com/help/hdlcoder/create-a-custom-hardware-platform.html

Callback functions available when define custom reference design (where you could execute your tcl):

https://www.mathworks.com/help/hdlcoder/ug/define-custom-reference-design-with-custom-parameters-and-callback-functions.html

Alternatively, if you only want to run IP core generation (without the later build steps). You could Export a script from HDL Workflow Advisor, and run the IP core generaiton workflow in command-line. This way you could then execute your Tcl using command line, so you can have one combined script to do both IP core generation and the Tcl execution.

https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-the-hdl-workflow-command-line-interface.html

Thanks,

Wang

[Alex Aronov]

Hi Wang,

Sorry for the delay in my reply. Thank you for your suggestion. It seams to me that it would do what I need. I need to verify it in my project but I would need few more days before I can get to do this.

Thanks,

alex

Answer 2

[Kiran Kintali]

In the HDL Workflow Advisor for Generic ASIC/FPGA workflow, in the FPGA Synthesis and Analysis > Create Project task, in the Additional source files field, enter the full path to the Tcl file manually, or by using the Add button. When HDL Coder™ creates the project, the specified Tcl script is executed to apply the synthesis project settings.

For your usecase custom reference design creation in IP core generation workflow would be more suitalbe. This workflow has steps for selecting a custom reference design and run build tasks which is what you are looking for. After Custom reference design creation you can execute additional callback functions to run Tcl scripts of your choice. See this example for additional details..

Can you reach out to tech support for additional features related to tcl specification? Thanks.

[Luca]

Hi Kiran,

Is it possible to do that from the SoC builder tool instead of the HDL Coder workflow? Or to indicate it through some configuration which is taken into account during the build of the system? I have been trying to do that but so far, no luck. Documentation of the SoC Blockset does not mention the topic, but as SoC Blockset makes use of HDL Coder, it should be possible.

Thanks.,

Luca.

[Kiran Kintali]

Here are some useful pointers.

• SoC Builder in SoC Blockset generates an entire system, and does not allow for customization to the vivado project (e.g. using Tcl files)
• HDL Coder based IP core generation inserts a generated IP core into a user-defined custom reference design, and therefore allows user customization for the project

If you have an existing SoC Blockset model, there is also an option to use the HDL Coder IP core generation workflow, as described here: https://www.mathworks.com/help/soc/ug/use-ipcore-workflow-to-target-soc-example.html

The differences between the two workflows are also explained more here: https://www.mathworks.com/help/soc/ug/soc-generation-workflows.html

Hope this helps.

[Luca]

Many thanks for the very useful information Kiran.

My design uses a RF Data Converter block, which is the one I am trying to customize with the tcl script. However, on the Extended Capabilities section of its page, it mentions to "use the SoC Builder tool", which is from SoC Blockset.

Does this means that it is not possible to customize my design because it uses the RF Data Converter block?

I tried generating code for it with HDL Coder and I got an error on R2022b: "Block 'soc_rfsoc_top/RF Data Converter/Stream to Sample2/Variant/On/Check Signal Attributes1' is not supported for HDL code generation." I will update and try the IP Core generation workflow, but I am not confident it will solve my issue.

Kind regards,

[Kiran Kintali]

The RF Data Converter block is supposed to be put outside of the DUT subsystem. Following example uses the RF Data Converter block and Simulink-canvas IP core generation workflow together: Multi-Channel Transceiver Using Xilinx RFSoC Device

If you are trying to modify the reference design to change the settings on the RF Data Converter in the reference design. You should consider reviewing these examples that show how to:

• Add a callback function to modify the vivado project using "PostCreateProjectFcn", https://www.mathworks.com/help/hdlcoder/ug/define-custom-reference-design-with-custom-parameters-and-callback-functions.html
• Create a new custom reference design. Document/Examples of creating a custom reference design to include your existing project into the workflow: https://www.mathworks.com/help/hdlcoder/create-a-custom-hardware-platform.html

Please reach out to tech support for additional help.