HDL Workflow Advisor Error

Hi,

I designed a Simulink model for the phase-locked loop using an adaptive scheme. I want to run this model on FPGA. I use the HDL coder of MATLAB to generate an HDL code. However, in the workflow advisor, I get an error mentioning that I cannot use the continuous sampling time. Nevertheless, I do not have any continuous block, and all sampling times are set to 1e-6s. It would be greatly appreciated if any could help me with the problem. I have attached a picture of my model and the error for more information.

Thanks!

Answer 1

[Kiran Kintali]

If you can share the model please add the attachment. If open the Sample time legend and do not see continuous sample time (0) feel free to reach out tech support and report an issue.

Continuous sample times are not supported for HDL Code Generation.

You need to discretize the model and use blocks in the DUT targeted for ASIC/FPGA.

It is a best practice to run the hdlsetup(<modelName>) command on the model.

https://www.mathworks.com/help/hdlcoder/ref/hdlsetup.html