How to update HDL verifier block when VHDL source changes its port definition?

I couldn't find a way to update the block when vhdl source change its source file. So, I have to manually add or remove those definition after re compile the vhdl source. I wonder if this is the only way to do so.

Answer 1

[Marc Erickson]

You have cited two ways to update the interface: Re-running the cosimulation wizard or using the block mask "Ports" tab and using "New" or "Delete" buttons. A third way is the "Autofill" button on that same "Ports" tab.

If the update is small, the "New" / "Delete" method on the Ports tab should be preferred. Adding a new signal or removing an existing one will not affect the remaining current connections to the surrounding model blocks.

There is no way for the tool to know how to connect new ports. If the updates are expected (e.g. a set of debug ports will be added), you can script model updates with commands such as "add_block" and "add_line". See https://www.mathworks.com/help/simulink/programmatic-modeling.html for more infomation.

[Poorren]

thanks for your information!

Answer 2

[Kiran Kintali]

https://www.mathworks.com/help/hdlverifier/ug/import-hdl-code-for-hdl-cosimulation-block.html

does your question refer to this workflow? Thanks

Cosimulation Type—Simulink Block

Open your model, and on the Apps tab, click HDL Verifier. Then, in the Mode section select HDL Cosimulation, and click Import HDL Files to open the Cosimulation Wizard.

[Poorren]

? why the answer is blank to me?

[Kiran Kintali]

refereshed the answer.

[Poorren]

Sorry, Sir!

My post may be not clear enough to you. My question is about how to update an existing HDL verifier simulation model. I use it to verify some very high level top module, which has lots of embedded modules. So, there's lots of test stimulus to this top module.

But, as debug and verification progress, some port definition of top module should be adjusted (add/remove). So, I have to recompile this module, and update the model. Until now, the only way to do so is to manually add/remove these port change, otherwise, I have to use cosimwizard to re-insert this module again, which implies lots of stimulus connection work. So, I wonder if there a way to update the module symbol automatically.

Thanks!