Different CIC decimator Response in normal simulation and FPGA implementation

I am trying to implement CIC decimator on ZYNQ706 FPGA. when I run the simulation in simulink it downsamples the signal and all the signal at output are at same position as were before the CIC decimator block. but when i implement the same model the signals position at the output of CIC block varies the position although the provided parameters are same as simulink simulation.. please let me know what could be the reasons for this odd output and how could i resolve the issue

Answer 1

[Bharath Venkataraman]

It would be helpful to see your model - are you using the CIC Decimation block? Did you build your own? Have you tired using the CIC Decimation HDL Optimized block?

Are you able to log the data going in and out of the CIC both in simulation and in hardware? That may give us a clue as to what's going on.

One other thing to do is to run the HDL with the testbench and make sure that passes. You can also do FPGA in the loop to verify that the design works as intended in the FPGA. HDL Verifier also allows a data capture option.

[muhammad ahmad]

well i am using CIC block. I have tried the HDL optimized as well . my concern is after downsampling the signal we had all the peaks present as before but after down sampling these peaks are present but not at the same position how can i onvestigate how should i applied bandpassfilter to process a specific signal . how do i know where this peak would lie after CIC decimation. attached is the simulink model to check

[Bharath Venkataraman]

I think your question about the design of the CIC decimation filter. If that is right, you can analyze the filter using filterDesigner. Use the multirate panel to design the

You can also create the equivalent filter using dsp.CICDecimator and fvtool or freqz to analyze the filter's responses.