How to add a custom parameter in the generated module with HDL Coder,simulink?
1 Ansicht (letzte 30 Tage)
Ältere Kommentare anzeigen
SHIYU SONG
am 9 Mär. 2022
Beantwortet: Kiran Kintali
am 17 Mär. 2022
Hi,
I want to design an uart_tx module, which has two parameters clk_frequency and Baud_rate.
In verilog, the correct code is as below:
module uart_tx
#(
parameter CLK_FRE = 50, //clock frequency(Mhz)
parameter BAUD_RATE = 115200 //serial baud rate
)
So, which block can generate it? Thanks.
0 Kommentare
Akzeptierte Antwort
Weitere Antworten (0)
Siehe auch
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!