Generate Test Cases for a Subsystem

You can analyze a subsystem within a model. This technique is good for large models, where you want to review the analysis in smaller, manageable reports. Following two methods help you to generate test cases for subsystem in different modes:

Generate Test Cases for Subsystems for Normal Mode

This example shows how to analyze the Controller subsystem in the sldvdemo_cruise_control model.

  1. Open the example model:

    openExample('sldv/CruiseControlTestGenerationExample',...
'supportingFile', 'sldvdemo_cruise_control');

  2. Right-click the Controller subsystem, and select Is Atomic.

    An atomic subsystem executes as a unit relative to the parent model. Subsystem block execution does not interleave with parent block execution. You can extract atomic subsystems for use as standalone models. After you set the parameter, other parameters become available, but you can ignore them.

  3. On the Simulation tab, in the File section, select Save > Save As and save the Cruise Control Test Generation model with a new name.

  4. Right-click the Controller subsystem, and in the Design Verifier app section , select Generate Tests for Subsystem.

  5. To start the subsystem analysis and generate test cases, click the Generate Tests button .

  6. The Simulink® Design Verifier™ software analyzes the subsystem. When the analysis is complete, view the analysis results for the Controller subsystem by clicking one of the following options:

    • Highlight analysis results on model

    • View tests in Simulation Data Inspector

    • Detailed analysis report

    • Create harness model

    • Export test cases to Simulink Test

    • Simulate tests and produce a model coverage report

    Note

    After processing a certain number of objectives, if the analysis stops, or if the analysis times out, you can use the Test Generation Advisor to better understand which subsystems are causing the problem. For more information, see Use Test Generation Advisor to Identify Analyzable Components.

  7. Review the results of the subsystem analysis and compare the results to the results of the full-model analysis as described in Perform Analysis on a Model:

    • The subsystem analysis analyzes the Controller as a standalone model.

    • The Controller subsystem contains all the test objectives in the Cruise Control Test Generation model. Both the analyzes generate the same test cases.

Generate Test Cases for Subsystems for Software-in-the-Loop Mode

Open Live Script

This example shows how to generate test cases for atomic subsystems in software-in-the-loop (SIL) mode by using the sldv_cruise_control_ats model.

Open the example model: sldv_cruise_control_ats.

model = "sldv_cruise_control_ats";
open_system(model);

1. In the Configuration Parameters dialog box, in the Code Generation pane and set System Target File to ert.tlc.

2. Right-click the PI Controller subsystem and click the Block Parameters button .

3. In the Block Parameters dialog box, under Code Generation set Function Packaging as Reusable function or Nonreusable function.

4. Click Hardware Implementation, then set Device vendor and Device type to the vendor and type of your SIL system. For this example, set Device vendor to Intel and Device type to x-86-32 (Linux).

  1. Generate the code for the target. For subsystem analysis in SIL mode, code needs to be generated before invoking test generation.

  2. If the test generation target is Code Generated as Top model, generate the code for the target by entering:

slbuild(model,'StandaloneCoderTarget');
### Unable to find Simulink cache file "sldv_cruise_control_ats.slxc".
### Searching for referenced models in model 'sldv_cruise_control_ats'.
### Total of 1 models to build.
### Starting build procedure for: sldv_cruise_control_ats
### Generating code and artifacts to 'Model specific' folder structure
### Generating code into build folder: /tmp/Bdoc26a_3146167_2116294/tp6e6e95c6/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw
### Invoking Target Language Compiler on sldv_cruise_control_ats.rtw
### Using System Target File: /mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/rtw/c/ert/ert.tlc
### Loading TLC function libraries
.......
### Initial pass through model to cache user defined code
.
### Caching model source code
...............................................................
### Writing header file sldv_cruise_control_ats_types.h
.
### Writing header file sldv_cruise_control_ats.h
### Writing header file rtwtypes.h
### Writing source file sldv_cruise_control_ats.c
### Writing header file sldv_cruise_control_ats_private.h
### Writing source file ert_main.c
.
### TLC code generation complete (took 2.623s).
### Saving binary information cache.
### Using toolchain: GNU gcc/g++ | gmake (64-bit Linux)
### Creating '/tmp/Bdoc26a_3146167_2116294/tp6e6e95c6/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw/sldv_cruise_control_ats.mk' ...
### Building 'sldv_cruise_control_ats': "/mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/bin/glnxa64/gmake"  -j 4 -l 4 -f sldv_cruise_control_ats.mk all
gcc -c -fwrapv -fPIC -O0 -DCLASSIC_INTERFACE=0 -DALLOCATIONFCN=0 -DTERMFCN=1 -DONESTEPFCN=1 -DMAT_FILE=0 -DMULTI_INSTANCE_CODE=0 -DINTEGER_CODE=0 -DMT=0  -DTID01EQ=0 -DMODEL=sldv_cruise_control_ats -DNUMST=1 -DNCSTATES=0 -DHAVESTDIO -DMODEL_HAS_DYNAMICALLY_LOADED_SFCNS=0 -I/tmp/Bdoc26a_3146167_2116294/tp6e6e95c6/sldv-ex49944916 -I/tmp/Bdoc26a_3146167_2116294/tp6e6e95c6/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw -I/mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/extern/include -I/mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/simulink/include -I/mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/rtw/c/src -I/mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/rtw/c/src/ext_mode/common -I/mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/rtw/c/ert -o "sldv_cruise_control_ats.o" "/tmp/Bdoc26a_3146167_2116294/tp6e6e95c6/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw/sldv_cruise_control_ats.c"
gcc -c -fwrapv -fPIC -O0 -DCLASSIC_INTERFACE=0 -DALLOCATIONFCN=0 -DTERMFCN=1 -DONESTEPFCN=1 -DMAT_FILE=0 -DMULTI_INSTANCE_CODE=0 -DINTEGER_CODE=0 -DMT=0  -DTID01EQ=0 -DMODEL=sldv_cruise_control_ats -DNUMST=1 -DNCSTATES=0 -DHAVESTDIO -DMODEL_HAS_DYNAMICALLY_LOADED_SFCNS=0 -I/tmp/Bdoc26a_3146167_2116294/tp6e6e95c6/sldv-ex49944916 -I/tmp/Bdoc26a_3146167_2116294/tp6e6e95c6/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw -I/mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/extern/include -I/mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/simulink/include -I/mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/rtw/c/src -I/mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/rtw/c/src/ext_mode/common -I/mathworks/devel/bat/filer/batfs2566-0/Bdoc26a.3146167/build/runnable/matlab/rtw/c/ert -o "ert_main.o" "/tmp/Bdoc26a_3146167_2116294/tp6e6e95c6/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw/ert_main.c"
### Creating standalone executable "../sldv_cruise_control_ats" ...
g++  -o ../sldv_cruise_control_ats sldv_cruise_control_ats.o ert_main.o  
### Created: "../sldv_cruise_control_ats"
### Successfully generated all binary outputs.
gmake: Nothing to be done for `all'.
### Successful completion of build procedure for: sldv_cruise_control_ats
### Simulink cache artifacts for 'sldv_cruise_control_ats' were created in '/tmp/Bdoc26a_3146167_2116294/tp6e6e95c6/sldv-ex49944916/sldv_cruise_control_ats.slxc'.

Build Summary

Top model targets:

Model                    Build Reason                                         Status                        Build Duration
==========================================================================================================================
sldv_cruise_control_ats  Information cache folder or artifacts were missing.  Code generated and compiled.  0h 0m 11.744s

1 of 1 models built (0 models already up to date)
Build duration: 0h 0m 13.282s

Note:

  • If the test generation target is Code Generated as Model Reference, generate the code for the target by entering:

% slbuild(model,'ModelReferenceCoderTargetOnly');

  • If there is a mismatch of the test generation target and the generated code interface target, then test generation returns an error.

  • If you generate a code for both targets, the test generation returns an error.

5. In the Apps tab, click Design Verifier. Then, in the Design Verifier tab next to Target, select Code Generated as Top Model. Generate tests by using one of these methods:

  • Right-click the PI Controller block, then click Generate Tests for Subsystems button to generate tests.

  • Select the PI Controller block by unpinning it from the toolstrip. Then, click Generate Tests.

  • Create a harness for the subsystem and then invoke test generation. Right-click the PI Controller block and in the Simulink Test app section , click the Add Test Harness button . Select the harness name and click OK.

Open the new harness. Then click Design Verifier and click Generate Tests.

Alternatively, you can use the code to generate the tests by entering:

opts = sldvoptions;

opts.TestgenTarget = Sldv.utils.Options.TestgenTargetGeneratedCodeStr;

[status, fileNames] = sldvrun(ssPath,opts,true);

6. Review the results of the subsystem analysis and compare the results to the results of the full-model analysis as described in Generate Test Cases for Subsystems for Normal Mode.