Detect Change

Detect change in signal value

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Libraries:
Simulink / Logic and Bit Operations
HDL Coder / Logic and Bit Operations

Description

The Detect Change block determines if an input signal does not equal its previous value. The initial condition determines the initial value of the previous input U/z.

This block supports only fixed-step discrete sample times.

Examples

Detect Change in Signal Values

This example shows how to detect a change in signal values using the Detect Change block. When the input from the Pulse Generator block remains the same, the Detect Change block outputs zero (false), indicating that there was no change in signal values. When the value of the Pulse Generator block changes, the Detect Change block outputs one (true) indicating that the current signal value does not equal its previous value.

Ports

Input

Port_1 — Input signal

signal value

Input signal, specified as a scalar, vector, or matrix.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | built-in integer | floating point

Output

Port_1 — Output signal

0 | 1

Output signal, true (equal to 1) when the input signal does not equal its previous value; false (equal to 0) when the input signal equals its previous value.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Parameters

Initial condition — Initial condition for the previous input

0 (default) | scalar | vector

Set the initial condition for the previous input U/z.

Programmatic Use

Block Parameter: vinit

Type: character vector

Values: scalar | vector

Default:'0'

Input processing — Specify sample- or frame-based processing

Elements as channels (sample based) (default) | Columns as channels (frame based)

Specify whether the block performs sample- or frame-based processing:

• Columns as channels (frame based) — Treat each column of the input as a separate channel (frame-based processing).

  Note

  Frame-based processing requires a DSP System Toolbox™ license.

  For more information, see Sample- and Frame-Based Concepts (DSP System Toolbox).

• Elements as channels (sample based) — Treat each element of the input as a separate channel (sample-based processing).

Use Input processing to specify whether the block performs sample- or frame-based processing. For more information about these two processing modes, see Sample- and Frame-Based Concepts (DSP System Toolbox).

Programmatic Use

Block Parameter: InputProcessing

Type: character vector

Values: 'Columns as channels (frame based)' | 'Elements as channels (sample based)'

Default: 'Elements as channels (sample based)'

Output data type — Data type of the output

boolean (default) | uint8

Set the output data type to boolean or uint8.

Programmatic Use

Block Parameter: OutDataTypeStr

Type: character vector

Values: 'boolean' | 'uint8'

Default: 'boolean'

Block Characteristics

Data Types	Boolean | double | enumerated | fixed point | integer | single
Direct Feedthrough	yes
Multidimensional Signals	yes
Variable-Size Signals	yes
Zero-Crossing Detection	no

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Generated code relies on memcpy or memset functions (string.h) under certain conditions.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a