Unit Delay Enabled (Obsolete)
Delay signal one sample period, if external enable signal is on
The Unit Delay Enabled block is not recommended. This block was removed from the Discrete library in R2016b. In new models, use the Delay block (with parameters set appropriately). Existing models that contain the Unit Delay Enabled block continue to work for backward compatibility.
Additional Math & Discrete / Additional Discrete (until R2016b)
The Unit Delay Enabled block delays a signal by one sample period when the external
E is on. While the enable is off, the block is
disabled. It holds the current state at the same value and outputs that value. The
enable signal is on when
E is not 0, and off when
E is 0.
You specify the block output for the first sampling period with the value of the Initial condition parameter.
You specify the time between samples with the Sample time
parameter. A setting of
-1 means that the block inherits the
Data Type Support
The Unit Delay Enabled block accepts signals of the following data types:
The output has the same data type as the input
u. For enumerated
signals, the Initial condition must be of the same enumerated type
as the input
For more information, see Data Types Supported by Simulink in the Simulink® documentation.
- Initial condition
Specify the initial output of the simulation.
- Sample time
Specify the time interval between samples. To inherit the sample time, set this parameter to
-1. See Specify Sample Time in the online documentation for more information.
Double | Single | Boolean | Base Integer | Fixed-Point | Enumerated
Specified in the Sample time parameter
HDL Code Generation Support
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic. For HDL code generation, it is recommended that you use the Unit Delay Enabled Synchronous (HDL Coder) block instead. This block uses the Unit Delay Enabled with the State Control (HDL Coder) block for synchronous hardware simulation behavior.
This block has a single, default HDL architecture.
HDL Block Properties
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline (HDL Coder).
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline (HDL Coder).
Unit Delay, Unit Delay Enabled External IC (Obsolete), Unit Delay Enabled Resettable (Obsolete), Unit Delay Enabled Resettable External IC (Obsolete), Unit Delay External IC (Obsolete), Unit Delay Resettable (Obsolete), Unit Delay Resettable External IC (Obsolete), Unit Delay With Preview Enabled (Obsolete), Unit Delay With Preview Enabled Resettable (Obsolete), Unit Delay With Preview Enabled Resettable External RV (Obsolete), Unit Delay With Preview Resettable (Obsolete), Unit Delay With Preview Resettable External RV (Obsolete)