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Simulink Cosimulation

HDL cosimulation with Simulink®

Blocks

HDL Cosimulation Cosimulate HDL design by connecting Simulink with HDL simulator
To VCD FileGenerate value change dump (VCD) file

Apps

Cosimulation WizardGenerate a cosimulation block or System object from existing HDL files

Functions

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nclaunchStart and configure Cadence Xcelium simulator for use with HDL Verifier software
vsimStart and configure ModelSim for use with HDL Verifier
hdlsimulinkLoad instantiated HDL module for cosimulation with Cadence Xcelium and Simulink
vsimulinkLoad instantiated HDL module for cosimulation with ModelSim and Simulink
breakHdlSimExecute stop command in HDL simulator from MATLAB
pingHdlSimBlock cosimulation until HDL simulator is ready
tclHdlSimExecute Tcl command in Xcelium or ModelSim simulator

Topics

Startup and Connection

Test Bench

Verification of Generated HDL Code with Cosimulation Test Bench (requires HDL Coder license)

Component Algorithm

Cosimulation with Simulink

HDL Simulator Interaction

  • Simulation Timescales
    The representation of simulation time differs significantly between the HDL simulator and Simulink.
  • Clock, Reset, and Enable Signals
    You can create rising-edge or falling-edge clocks, resets, or clock enable signals that apply internal stimuli to your model under cosimulation.
  • Simulation Speed Improvement Tips
    Provides suggestions for optimizing your cosimulation performance.
  • Supported Data Types
    If your HDL application needs to send HDL data to a MATLAB function, you may first need to convert the data to a type supported by MATLAB and the HDL Verifier software.
  • Race Conditions in HDL Simulators
    Describes ways to avoid race conditions in hardware cosimulations with MATLAB and Simulink software.

Recording Signal State Transitions for Post-Processing