Cosimulate HDL design by connecting Simulink with HDL simulator
HDL Verifier / For Use with Cadence Incisive
HDL Verifier / For Use with Mentor Graphics ModelSim
The HDL Cosimulation block cosimulates a hardware component by applying input signals to and reading output signals from an HDL model under simulation in the HDL simulator. You can use this block to model a source or sink device by configuring the block with input or output ports only.
You can configure these options on the block:
Mapping of the input and output ports of the block to correspond with signals (including internal signals) of an HDL module. You must specify a sample time for each output port. You can optionally specify a data type for each output port.
Type of communication and communication settings used to exchange data between simulators.
The timing relationship between units of simulation time in Simulink® and the HDL simulator.
Rising-edge or falling-edge clocks to apply to your model. You can specify the period for each clock signal.
Tcl commands to run before and after the simulation.
Compatibility with Simulink Code Generation
This block participates in HDL code generation with HDL Coder™. The coder generates an interface to your manually written or legacy HDL code. It does not participate in C code generation with Simulink Coder™.
The ports shown on the block correspond with signals from your HDL design running in the HDL simulator. You can add and remove ports, and configure their data types and sample times, by changing the block parameters. The Ports tab displays the HDL signals that correspond to the ports. You can add, remove, and change the order of the ports. Use the Auto Fill button to fill the table via a port information request to the HDL simulator. This request returns port names and information from your HDL design running in the HDL simulator. See “Get Signal Information from HDL Simulator” for a detailed description of this feature.
All signals that you specify when you configure the HDL Cosimulation block must have read/write access in the HDL simulator. Refer to the HDL simulator product documentation for details.
When you import VHDL® signals from the HDL simulator, HDL Verifier™ returns the signal names in all capitals.