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Model Design and Compatibility Guidelines - By Numbered List

The HDL modeling guidelines are a set of recommended guidelines that you can follow when creating Simulink® model for code generation with HDL Coder™. The model design and compatibility guidelines consist of guidelines for basic block usage, clock and reset signals, buses and vectors, and subsystem and hierarchical designing. Each modeling guideline for HDL code generation has a different level of severity that indicates the levels of compliance requirements. To learn more about these severity levels, see HDL Modeling Guidelines Severity Levels.

These tables list the model design and compatibility guidelines in HDL Coder. These guidelines start from 1.1 and are divided into subsections. In the table, you see that certain guidelines have an associated model check. You can follow the modeling pattern recommended for these guidelines by running that check in the HDL Code Advisor. To learn more about the HDL Code Advisor, see Check HDL Compatibility of Simulink Model Using HDL Code Advisor.

Guidelines 1.1: Basic Settings

Guidelines 1.2: DUT Subsystem and Hierarchical Modeling

Guidelines 1.3: Guidelines for Vectors and Buses

Guideline IDTitleSeverityAssociated Model Check/Coding Standard Rule
1.3.1Modeling Requirements for Matrices MandatoryModel Check: Check for large matrix operations
1.3.2Avoid Generating Ascending Bit Order in HDL Code From Vector SignalsStrongly RecommendedNone
1.3.3Use Bus Signals to Improve Readability of Model and Generate HDL CodeInformativeNone

Guidelines 1.4: Guidelines for Clock Bundle Signals

Guidelines 1.5: Modeling Guidelines for Native Floating Point

Guideline IDTitleSeverityAssociated Model Check/Coding Standard Rule
1.5.1Modeling with Native Floating Point RecommendedNone

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