Synthesis and Timing Analysis

Generate synthesis scripts and retrieve synthesis results

You can enable or disable the generation of compilation, simulation, or synthesis scripts by using the makehdl or makehdltb functions and then customize the names and content of the generated script files. You can also generate Tcl commands for specific synthesis tools by specifying synthesis objectives such as area optimization, compile optimization, or speed optimization in the HDL Workflow Advisor or in the HDL Workflow command line interface.

Functions

hdlsetuptoolpath Set up system environment to access FPGA synthesis software

Topics

Structure of Generated Script Files
A generated EDA script consists of an initialization phase, command-per-file phase, and a termination phase.
Properties for Controlling Script Generation
Enable or disable script generation and customize the names and content of generated script files by using the makehdl or makehdltb functions.
Synthesis Objective to Tcl Command Mapping
Tool-specific Tcl commands that correspond to the HDL Workflow synthesis objectives.
Generate Scripts for Compilation, Simulation, and Synthesis
Command line properties and GUI options for customizing script files.
Configure Compilation, Simulation, Synthesis, and Lint Scripts
Configure the script file generation by using the EDA Tool Scripts pane.
Add Synthesis Attributes
Synthesis attributes in generated code.
Configure Synthesis Project Using Tcl Script
Add Tcl script that configures your synthesis project.