coder.HdlConfig
HDL codegen
configuration object
Description
A coder.HdlConfig
object contains the configuration parameters
that the HDL codegen
function requires to generate HDL code. To pass this
object to the codegen
function, use the -config
option.
Creation
Description
hdlcfg =
coder.config("hdl")
creates a
coder.HdlConfig
object for HDL code generation.
Properties
General
HDLCodingStandard
— HDL coding standard to follow
'None'
(default) | 'Industry'
HDL coding standard to follow when generating code, specified as a character vector or string array. Generates a compliance report showing errors, warnings, and messages.
Example: 'Industry'
"Industry"
Data Types: char
| string
HDLCodingStandardCustomizations
— HDL coding standard rules and report customizations
none (default) | HDL coding standard customization object
HDL coding standard rules and report customizations, specified by using HDL Coding
Standard Customization Properties. For more information, see HDL Coding Standard Customization Properties. If you want to customize the
coding standard rules and report, you must set HDLCodingStandard
to
"Industry"
.
TargetLanguage
— Target language of the generated code
'VHDL'
(default) | 'Verilog'
| 'SystemVerilog'
| 'SystemC'
| 'SynthesizableC++'
Target language of the generated code, specified as a character vector or string array.
Example: 'Verilog'
"Verilog"
Data Types: char
| string
TestBenchName
— Test bench function name
''
(default) | 'Testbench name
'
| "Testbench name
"
Testbench name
'Testbench name
"Test bench function name, specified as a character vector or string array. You must specify a test bench.
Data Types: char
| string
Workflow
— Code generation workflow
"Generic ASIC/FPGA"
(default) | "FPGA Turnkey"
| "High Level Synthesis"
| "IP Core Generation"
HDL code generation workflow, specified as a character vector or string array.
Example: "High Level Synthesis"
Workflow
GenerateCosimTestBench
— Option to generate a cosimulation test bench
false
or 0
(default) | true
or 1
Option to generate a cosimulation test bench, specified as a numeric or logical
1
(true) or 0
(false).
Data Types: logical
GenerateFILTestBench
— Option to generate FIL test bench
false
or 0
(default) | true
or 1
Option to generate a FIL test bench, specified as a numeric or logical
1
(true) or 0
(false).
Data Types: logical
GenerateHDLTestBench
— Option to generate an HDL test bench
false
or 0
(default) | true
or 1
Option to generate an HDL test bench, specified as a numeric or logical
1
(true) or 0
(false).
Data Types: logical
SimulateCosimTestBench
— Option to simulate generated cosimulation test bench
false
or 0
(default) | true
or 1
Option to simulate a generated cosimulation test bench, specified as a numeric or
logical 1
(true) or 0
(false). This option is
ignored if GenerateCosimTestBench
is
false
.
Data Types: logical
SimulateFILTestBench
— Option to simulate generated cosimulation test bench
false
or 0
(default) | true
or 1
Option to simulate a generated cosimulation test bench, specified as a numeric or
logical 1
(true) or 0
(false). This option is
ignored if GenerateCosimTestBench
is
false
.
Data Types: logical
SimulateGeneratedCode
— Option to simulate generated code
false
or 0
(default) | true
or 1
Option to simulate generated code, specified as a numeric or logical
1
(true) or 0
(false).
Data Types: logical
SynthesizeGeneratedCode
— Option to synthesize generated code
false
or 0
(default) | true
or 1
Option to synthesize generated code, specified as a numeric or logical
1
(true) or 0
(false).
Data Types: logical
HLSTestBenchStimulus
— High-Level Synthesis (HLS) test bench function name
'HDL Test bench stimulus'
(default) | 'Test bench with random input stimulus'
HLS test bench function name, specified as a character vector or string array. Specify the test bench for HLS code generation.
Example: 'Test bench with random input stimulus'
Data Types: char
| string
Target Tool Selection
CosimClockEnableDelay
— Time delay before clock enable
0
(default)
Time (in clock cycles) between deassertion of reset and assertion of clock enable.
Data Types: int32
CosimClockHighTime
— Time that clock is high
5
(default)
The number of nanoseconds the clock is high.
Data Types: int32
CosimClockLowTime
— Time that clock is low
5
(default)
The number of nanoseconds the clock is low.
Data Types: int32
CosimHoldTime
— Hold time for input signals and forced reset signals
2
(default)
The hold time for input signals and forced reset signals, specified in nanoseconds.
Data Types: int32
CosimLogOutputs
— Option to log and plot outputs of the reference design function and HDL simulator
false
or 0
(default) | true
or 1
Option to log and plot outputs of the reference design function and HDL simulator,
specified as a numeric or logical 1
(true) or 0
(false).
Data Types: logical
CosimResetLength
— Cosimulation reset length
2
(default)
Specify the time (in clock cycles) between assertion and deassertion of reset.
Data Types: int32
CosimRunMode
— HDL simulator run mode during simulation
'Batch'
(default) | 'GUI'
HDL simulator run mode during simulation, specified as a character vector or string
array. When in Batch
mode, you do not see the HDL simulator UI. The
HDL simulator shuts down after simulation.
Example: 'GUI'
"GUI"
Data Types: char
| string
CosimTool
— HDL Simulator
'ModelSim'
(default) | 'Incisive'
| 'Vivado Simulator'
HDL simulator for the generated cosim test bench, specified as a character vector or string array.
Example: 'Incisive'
"Incisive"
Data Types: char
| string
FILAdditionalFiles
— List of additional source files to include
''
(default) | 'Additional source files
'
Additional source files
'List of additional source files to include, specified as a character vector or string array. Separate file names by using a semicolon (;).
Data Types: char
| string
FILBoardIPAddress
— IP address of the FPGA board
'192.168.0.2'
(default)
IP address of the FPGA board, specified as a character vector or string array. You must enter a valid IP address.
Data Types: char
| string
FILBoardMACAddress
— MAC address of the FPGA board
'00-0A-35-02-21-8A'
(default)
MAC address of the FPGA board, specified as a character vector or string array. You must enter a valid MAC address.
Data Types: char
| string
FILBoardName
— FPGA board name
'Choose a board'
(default) | 'A board name
'
A board name
'FPGA board name, specified as a character vector or string array. You must override the default value and specify a valid board name.
Data Types: char
| string
FILLogOutputs
— Option to log and plot outputs of the reference design function and FPGA
false
or 0
(default) | true
or 1
Option to log and plot outputs of the reference design function and FPGA, specified
as a numeric or logical 1
(true) or 0
(false).
Data Types: logical
SimulationTool
— Simulation tool name
'ModelSim'
(default) | 'ISIM'
Simulation tool name, specified as a character vector or string array.
Example: 'ISIM'
"ISIM"
Data Types: char
| string
SynthesisTool
— Synthesis tool name
''
(default) | 'Xilinx Vivado'
| 'Altera Quartus II'
| 'Microsemi Libero SoC'
| 'Intel Quartus Pro'
| 'Xilinx ISE'
| 'Cadence Stratus'
| 'Xilinx Vitis HLS'
Synthesis tool name, specified as a character vector or string array.
Example: 'Xilinx Vivado'
"Xilinx Vivado"
Data Types: char
| string
SynthesisToolChipFamily
— Synthesis target chip family name
''
(default) | 'Family name
'
Family name
'Synthesis target chip family name, specified as a character vector or string array.
Data Types: char
| string
SynthesisToolDeviceName
— Synthesis target device name
''
(default) | 'Device name
'
Device name
'Synthesis target device name, specified as a character vector or string array.
Data Types: char
| string
SynthesisToolPackageName
— Synthesis target package name
''
(default) | 'Package name
'
Package name
'Synthesis target package name, specified as a character vector or string array.
Data Types: char
| string
SynthesisToolSpeedValue
— Synthesis target speed
''
(default) | 'Speed value
'
Speed value
'Synthesis target speed, specified as a character vector or string array.
Data Types: char
| string
TargetFrequency
— Target clock frequency
0 (default)
Specify the target frequency, in MHz, of the clock wired to the clock input of the generated HDL design. This frequency is the same as the output clock frequency of the clock module. Adaptive pipelining takes into account the target frequency that you set to improve the frequency of your design.
Data Types: double
Code Style
InitializeBlockRAM
— Option to initialize block RAM
true
or 1
(default) | false
or 0
Option to initialize block RAM to 0
for simulation, specified as
a numeric or logical 1
(true) or 0
(false).
Data Types: logical
InlineConfigurations
— Option to include inline configurations in generated VHDL code
true
or 1
(default) | false
or 0
Option to include inline configurations in generated VHDL code, specified as a
numeric or logical 1
(true) or 0
(false).
When true
, include VHDL configurations in files that instantiate
a component.
When false
, suppress the generation of configurations and require
user-supplied external configurations. Set to false
if you are
creating your own VHDL configuration files.
Data Types: logical
TimingControllerPostfix
— Timing controller postfix
'_tc'
(default) | 'Postfix
'
Postfix
'Postfix to append to the design name to form the name of the timing controller, specified as a character vector or string array.
Data Types: char
| string
VHDLLibraryName
— Target library name for generated VHDL® code
'work'
(default) | 'Library name
'
Library name
'Target library name for generated VHDL code, specified as a character vector or string array.
Data Types: char
| string
Clocks
ClockEdge
— Active clock edge
'Rising'
(default) | 'Falling'
Active clock edge, specified as a character vector or string array.
Example: 'Rising'
"Rising"
Data Types: char
| string
Oversampling
— Oversampling factor
1 (default) | integer greater than or equal to 1
Oversampling factor, specified as an integer greater than or equal to 1. Specify the frequency of global oversampling clock as a multiple of the design base clock rate.
Data Types: int32
TimingControllerArch
— Timing controller architecture
'default'
(default) | 'resettable'
Timing controller architecture, specified as one of these options:
TimingControllerArch Value | Description |
---|---|
| Generate a timing controller without a reset. This setting generates a timing controller code file as its own HDL file and instantiates the timing controller in the DUT at the top level. |
| Generate a timing controller in the DUT with a reset. This setting generates a timing controller code file as its own HDL file and instantiates the timing controller in the DUT at the top level. |
Example: 'resettable'
Data Types: char
| string
Ports
IOThreshold
— Maximum number of I/O pins for FPGA deployment
5000 (default) | positive integer
Maximum number of I/O pins for FPGA deployment, specified as an integer. Specify the
maximum number of I/O pins for your target FPGA. If the DUT pin count in the generated
code exceeds the value of this parameter, HDL Coder™ generates the message specified by the
TreatIOThresholdAs
parameter in the HDL Conformance Report.
Data Types: int32
TreatIOThresholdAs
— Message to return if DUT pin count exceeds I/O threshold
'Error'
(default) | 'Warning'
| 'None'
Message to return if DUT pin count exceeds I/O threshold, specified as a character
vector or string array. Specify the type of message generated when the DUT pin count in
the generated code exceeds the maximum number of I/O pins threshold set by the
IOThreshold
parameter.
Example: 'Warning'
"Warning"
Data Types: char
| string
Optimizations
AdaptivePipelining
— Option to insert adaptive pipeline registers in your design
false
or 0
(default) | true
or 1
Option to insert adaptive pipeline registers in your design, specified as a numeric
or logical 1
(true) or 0
(false). Enable adaptive
pipelining to insert pipeline registers to the blocks in your design, reduce the area
usage, and maximize the achievable clock frequency on the target FPGA device.
When you specify this parameter, specify the Synthesis Tool in the Select Code Generation Target task. If your design has multipliers, specify the Synthesis Tool and the Target Frequency (MHz) for adaptive pipeline insertion.
Data Types: logical
AdderSharingMinimumBitwidth
— Minimum bit width for shared adders
0
(default) | integer greater than or equal to 2
Minimum bit width for shared adders, specified as a positive integer.
If ShareAdders
is true
and
ResourceSharing
is greater than 1, share adders only if adder bit
width is greater than or equal to
AdderSharingMinimumBitwidth
.
Data Types: int32
AggressiveDataflowConversion
— Option to use dataflow representation for MATLAB® functions
false
or 0
(default) | true
or 1
Option to use dataflow representation for MATLAB functions, specified as a numeric
or logical 1
(true) or 0
(false). Transform the
control flow algorithm of the MATLAB code inside a MATLAB function to a dataflow representation. Set this property to
true
for optimizations and options that use dataflow
representation, such as frame-to-sample conversion and native floating-point
optimizations.
If you set both AggressiveDataflowConversion
and
GenerateMLFcnBlock
to true
, you can generate a
functionally equivalent Simulink® model of your MATLAB function design that contains Simulink blocks, which is comparable to designing the algorithm with Simulink.
Data Types: logical
AllowDelayDistribution
— Option to allow design delay distribution
true
or 1
(default) | false
or 0
Option to allow distributed pipelining and delay absorption to move design delays,
specified as a numeric or logical 1
(true) or 0
(false). Set this parameter to 0
to prevent distributed pipelining
and delay absorption from moving design delays.
Persistent variables and dsp.Delay
System objects
are design delays.
Data Types: logical
BalanceClockRateOutputPorts
— Option to balance clock-rate pipelined DUT output ports
false
or 0
(default) | true
or 1
Option to balance clock-rate pipelined DUT output ports, specified as a numeric or
logical 1
(true) or 0
(false). Synchronize the DUT
outputs while satisfying the highest-latency requirements of the outputs. Apply this
option when interfacing your logic with a valid signal interface to align the output of
the logic path and valid signal path.
Data Types: logical
ClockRatePipelineOutputPorts
— Option to allow clock-rate pipelining of DUT output ports
false
or 0
(default) | true
or 1
Option to allow clock-rate pipelining of DUT output ports, specified as a numeric or
logical 1
(true) or 0
(false). Set this property
to true
to produce the DUT outputs as soon as possible by passing the
outputs from the DUT at the clock rate rather than the data rate.
Data Types: logical
ClockRatePipelining
— Option to insert pipeline registers at clock rate
true
or 1
(default) | false
or 0
Option to insert pipeline registers at the clock rate, specified as a numeric or
logical 1
(true) or 0
(false). Use clock-rate
pipelining to insert pipeline registers at a clock rate that is faster than the data
rate. This optimization improves the clock frequency and reduces the area usage without
introducing additional latency. Clock-rate pipelining does not
affect existing design delays in your design.
Data Types: logical
DistributedPipelining
— Option to distribute pipeline registers
false
or 0
(default) | true
or 1
Option to distribute pipeline registers, specified as a numeric or logical
1
(true) or 0
(false). When enabled, HDL Coder moves registers within your design to reduce the critical path.
Data Types: logical
PipelineDistributionPriority
— Priority for distributed pipelining and delay absorption algorithms
'NumericalIntegrity'
(default) | 'Performance'
Priority for distributed pipelining and delay absorption algorithms, specified as one of these options:.
PipelineDistributionPriority
Value | Description |
---|---|
'NumericalIntegrity' (default) | Prioritize numerical integrity when distributing pipeline registers. This option uses a conservative retiming algorithm that does not move registers across a component if the functional equivalence to the original design is unknown. |
'Performance' | Prioritize performance over numerical integrity. Use this option if your design requires a higher clock frequency and the MATLAB behavior does not need to strictly match the generated code behavior. This option uses a more aggressive retiming algorithm that moves registers across a component even if the modified design’s functional equivalence to the original design is unknown. |
Example: 'NumericalIntegrity'
"NumericalIntegrity"
Data Types: char
| string
InputPipeline
— Number of input pipeline register stages
0
(default) | integer greater than 0
Specify the number of input pipeline register stages. When
DistributedPipelining
is enabled, these registers can be
distributed through the design.
Data Types: int32
LoopOptimization
— Loop optimization
'LoopNone'
(default) | 'StreamLoops'
| 'UnrollLoops'
Loop optimization in generated code, specified as a character vector or string array. See Optimize MATLAB Loops.
LoopOptimization Value | Description |
---|---|
LoopNone | Do not optimize loops in generated code. |
StreamLoops | Stream loops. |
UnrollLoops | Unroll loops. |
Example: 'StreamLoops'
"StreamLoops"
Data Types: char
| string
MapPersistentVarsToRAM
— Map persistent array variables to RAM
true
or 1
(default) | false
or 0
Map persistent array variables to RAM, specified as a numeric or logical
1
(true) or 0
(false). Use this property to
optimize area and save resources on your target device by mapping persistent arrays to
block RAM.
To map these persistent arrays to block RAMs, the RAM size must be greater than or equal to the RAM mapping threshold. See RAMThreshold.
Data Types: logical
MapPipelineDelaysToRAM
— Map pipeline registers in generated HDL code to RAM
false
or 0
(default) | true
or 1
Map pipeline registers in generated HDL code to RAM, specified as a numeric or
logical 1
(true) or 0
(false). Use this property
to map the pipeline registers inserted by pipelining and resource sharing optimizations
and block implementations to RAM. You can save area on your target device by mapping
pipeline registers to RAM.
To map these registers to block RAMs, the RAM size must be greater than or equal to the RAM mapping threshold. See RAMThreshold.
Data Types: logical
MinimizeClockEnables
— Option to omit generation of clock enable logic
false
or 0
(default) | true
or 1
Option to omit generation of clock enable logic, specified as a numeric or logical
1
(true) or 0
(false).
When false
(default), generate clock enable logic.
When true
, omit generation of clock enable logic wherever
possible.
Data Types: logical
MultiplierPartitioningThreshold
— Maximum input bit width for hardware multipliers
none (default) | integer greater than or equal to 2
Specify maximum input bit width for hardware multipliers. If a multiplier input bit width is greater than this threshold, HDL Coder splits the multiplier into smaller multipliers.
To improve your hardware mapping results, set this threshold to the input bit width of the digital signal processor (DSP) or multiplier hardware on your target device.
Data Types: int32
MultiplierSharingMinimumBitwidth
— Minimum bit width for shared multipliers
none (default) | integer greater than or equal to 2
Minimum bit width for shared multipliers, specified as a positive integer.
If ShareMultipliers
is true
and
ResourceSharing
is greater than 1, share multipliers only if
multiplier bit width is greater than or equal to
MultiplierSharingMinimumBitwidth
.
Data Types: int32
OutputPipeline
— Number of output pipeline register stages
0
(default) | integer greater than 0
Specify the number of output pipeline register stages. When
DistributedPipelining
is enabled, these registers can be
distributed through the design.
Data Types: int32
RAMThreshold
— Minimum RAM size for mapping persistent array variables and pipeline delays to block RAM
'256'
(default) | string array | character vector
Minimum RAM size for mapping persistent array variables and pipeline delays to block RAM, specified as a string array or character vector.
Specify the RAM mapping threshold by using either:
A string array or character vector of a single positive integer to map persistent array variables to RAM if the RAM size is greater than this threshold. The unit is bits. To calculate the total RAM size for persistent arrays, use this formula:
RAMSize = Array size * Word length * Complexity
Complexity
is 2 for a complex data type or 1 for a real datatype. To calculate the total RAM size for delays, use this formula:RAMSize = Delay length * Word length * Vector length * Complexity
A string array or character vector of format
MxN
that specifies two thresholds to define the shape of the data to map to RAM, whereM
is for array size (for persistent arrays) or delay length (for delays) andN
is for word length or bit width of the data type.
Example: "256"
Example: "500x50"
Data Types: string
| char
RegisterInputs
— Option to insert pipeline register at each DUT input
false
or 0
(default) | true
or 1
Option to insert a pipeline register at each DUT input, specified as a numeric or
logical 1
(true) or 0
(false). Distributed
pipelining does not move these registers.
Data Types: logical
RegisterOutputs
— Option to insert pipeline register at each DUT output
false
or 0
(default) | true
or 1
Option to insert a register at each DUT output, specified as a numeric or logical
1
(true) or 0
(false). Distributed pipelining
does not move these registers.
Data Types: logical
ShareAdders
— Option to share adders
false
or 0
(default) | true
or 1
Option to share adders, specified as a numeric or logical 1
(true) or 0
(false). If true
, share adders when
ResourceSharing
is greater than 1 and adder bit width is greater
than or equal to AdderSharingMinimumBitwidth
.
Data Types: logical
ShareMultipliers
— Option to share multipliers
true
or 1
(default) | false
or 0
Option to share multipliers, specified as a numeric or logical 1
(true) or 0
(false). If true
, share multipliers
when ResourceSharing
is greater than 1 and multiplier bit width is
greater than or equal to MultiplierSharingMinimumBitwidth
.
Data Types: logical
Floating Point
FloatingPointLibrary
— Floating point library name
'None'
(default) | 'NativeFloatingPoint'
Floating-point library name, specified as a character vector or string array.
Example: 'NativeFloatingPoint'
Data Types: char
| string
FloatingPointTargetConfiguration
— Floating point target configuration
[ ] (default) | hdlcoder.FloatingPointTargetConfig
object
Floating point target configuration when using native floating point for HDL code
generation, specified as an hdlcoder.FloatingPointTargetConfig
object. To configure the floating point target, see hdlcoder.FloatingPointTargetConfig
. To generate HDL code from a MATLAB function, you can only set the native floating point properties
HandleDenormals
, LatencyStategy
, and
MantissaMultiplyStrategy
in the
hdlcoder.FloatingPointTargetConfig
class.
Example: hdlcfg.FloatingPointTargetConfiguration =
hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT')
, where
hdlcfg
is a coder.HdlConfig
object. See
createFloatingPointTargetConfig
.
Data Types: hdlcoder.FloatingPointTargetConfig
Advanced Coding
GenerateMLFcnBlock
— Option to generate Simulink model from MATLAB function
false
or 0
(default) | true
or 1
Option to generate a Simulink model from your MATLAB function, specified as a numeric or logical 1
(true) or
0
(false). You must have a Simulink license.
If you set AggressiveDataflowConversion
to
false
, this parameter generates a MATLAB Function
block to use in a Simulink model.
If you set AggressiveDataflowConversion
to
true
, this parameter generates a functionally equivalent
Simulink model of your MATLAB function design that contains Simulink blocks that perform the algorithm designed in your MATLAB function. This model is similar to a generated model in the Simulink-to-HDL workflow.
Data Types: logical
InstantiateFunctions
— Option to generate instantiable HDL code modules
false
or 0
(default) | true
or 1
Option to generate instantiable HDL code modules from functions, specified as a
numeric or logical 1
(true) or 0
(false).
Data Types: logical
SaturateOnIntegerOverflow
— Integer overflow support
true
(default) | false
Integer overflow support, specified as one of the values in this table.
Value | Description |
---|---|
true | This value is the default value. The code generator produces code to handle integer overflow. Overflows saturate to either the minimum or maximum value that the data type can represent. |
false | The code generator does not produce code to handle integer
overflow. Do not set |
This parameter applies only to MATLAB built-in integer types. It does not apply to doubles, singles, or fixed-point data types.
TreatRealsInGeneratedCodeAs
— Check for reals in generated HDL code
'Error'
(default) | 'Warning'
| 'None'
Check for reals in the generated HDL code, specified as a character vector or string array.
Value | Description |
---|---|
None | Do not check for reals in the generated HDL code. |
Warning | Checks and warns of presence of real data types in the generated HDL code. Real data types in the generated HDL code are not synthesizable on target FPGA devices. |
Error | Checks and generates an error if the generated HDL code uses real data
types. If you are generating code for simulation purposes and not for
synthesizing your design, you can change this setting
to Warning or None . To
generate synthesizable HDL code, set the Floating Point IP
Library to Native Floating
Point . |
Example: 'None'
"None"
Data Types: char
| string
Test Bench
SimulationIterationLimit
— Simulation iteration limit
-1
(default) | positive integer
Maximum number of simulation iterations during test bench generation. This property
affects only test bench generation, not simulation during fixed-point conversion. When
the value is -1
(default), no maximum
number of simulation iterations is set.
Data Types: int32
UseFileIOInTestBench
— Option to use data files for test bench input and output data
true
or 1
(default) | false
or 0
Option to create and use data files for reading and writing test bench input and
output data, specified as a numeric or logical 1
(true) or
0
(false).
Data Types: logical
Lint Script
HDLLintCmd
— HDL lint script command
''
(default)
If you set HDLLintTool
to Custom
, you must
use %s
as a placeholder for the HDL file name in the generated Tcl
script. Specify HDLLintCmd
as a string array or character vector by
using this
format:
custom_lint_tool_command -option1 -option2 %s
Data Types: char
| string
HDLLintInit
— HDL lint script initialization name
''
(default)
HDL lint script initialization name, specified as a character vector or string array.
Data Types: char
| string
HDLLintTerm
— HDL lint script termination name
''
(default)
HDL lint script termination name, specified as a character vector or string array.
Data Types: char
| string
HDLLintTool
— HDL lint tool script
'None'
(default) | 'AscentLint'
| 'Leda'
| 'SpyGlass'
| 'Custom'
HDL lint tool script to generate, specified as a character vector or string array.
Example: 'SpyGlass'
"SpyGlass"
Data Types: char
| string
Frame to Sample Conversion
FrameToSampleConversion
— Option to enable frame to sample conversion
false
or 0
(default) | true
or 1
Option to enable frame-to-sample conversion, specified as a numeric or logical
1
(true) or 0
(false). If your MATLAB function is not synthesizable because it requires a large amount of I/O,
this optimization can reduce the I/O in the design and generate synthesizable HDL code.
The frame-to-sample conversion converts matrix inputs to smaller samples by streaming
the input signal for HDL code generation to reduce the I/O that handles a large input
signal. For more information, see HDL Code Generation from Frame-Based Algorithms.
To enable this property, set AggressiveDataflowConversion
to
true
.
Data Types: logical
DelaySizeThreshold
— Delay size threshold for external memory
10000
(default) | positive numeric value
Delay size threshold for external memory, specified as a positive numeric value. Specify a threshold size in kilobytes to map large integer delays to input and output DUT ports. Use this property to offload large delays to external memory outside of your FPGA. If you map large delays to external memory, you cannot generate a test bench.
To enable this property, set FrameToSampleConversion
to
true
.
Data Types: double
InputFIFOSize
— Register size of generated input FIFOs
10
(default) | integer greater than or equal to 4
Register size of generated input FIFOs, specified as an integer greater than or equal to 4. Use this parameter to specify the register size of the generated input FIFOs around the streaming matrix partitions. The frame-to-sample conversion generates an input FIFO for every input to the MATLAB function that has a sampled-based input signal.
To enable this property, set FrameToSampleConversion
to
true
.
Data Types: int32
InputProcessingOrder
— Order to process incoming frame data
'RowMajor'
(default) | 'ColumnMajor'
Order to process incoming frame data, specified as 'RowMajor'
or
'ColumnMajor'
. Choose between row-major and column-major ordering
for the frame inputs that the frame-to-sample conversion optimization converts to sample
inputs. This setting affects how the data is streamed into the device under test (DUT),
but does not change the behavior of the generated DUT.
Set this property to 'RowMajor'
to traverse the input frame data
for the frame-to-sample conversion using row-major ordering, which traverses the data
from left to right and then top to bottom across the frame-based input matrix.
Set this property to 'ColumnMajor'
to traverse the input frame
data for the frame-to-sample conversion using column-major ordering, which traverses the
data from top to bottom and then left to right across the frame-based input
matrix.
To enable this property, set FrameToSampleConversion
to
true
.
Data Types: char
| string
OutputFIFOSize
— Register size of generated output FIFOs
10
(default) | integer greater than or equal to 4
Register size of the generated output FIFOs, specified as an integer greater than or equal to 4. Use this parameter to specify the register size of the generated output FIFOs around the streaming matrix partitions. The frame-to-sample conversion generates an output FIFO for every output of the MATLAB function that has a sampled-based output signal.
To enable this property, set FrameToSampleConversion
to
true
.
Data Types: int32
SamplesPerCycle
— Samples per cycle
1
(default) | integer greater than or equal to 1
Samples per cycle, specified as an integer greater than or equal to 1. Use this parameter to specify the size of the signals after the frame-to-sample conversion streams them. The streamed input signal is either a scalar (one sample per cycle) or 1-D vectors with N elements (N samples per cycle).
To enable this property, set FrameToSampleConversion
to
true
.
Data Types: int32
Examples
Generate Verilog Code from MATLAB Code
Create a coder.HdlConfig
object hdlcfg
.
hdlcfg = coder.config("hdl"); % Create a default "hdl" config
Set the test bench name. In this example, the test bench function name is
mlhdlc_dti_tb
.
hdlcfg.TestBenchName = "mlhdlc_dti_tb";
Set the target language to Verilog®.
hdlcfg.TargetLanguage = "Verilog";
Generate HDL code from your MATLAB design. In this example, the MATLAB design function name is mlhdlc_dti
.
codegen -config hdlcfg mlhdlc_dti
Generate SystemVerilog Code from MATLAB Code
Create a coder.HdlConfig
object hdlcfg
.
hdlcfg = coder.config("hdl"); % Create a default "hdl" config
Set the test bench name. In this example, the test bench function name is
mlhdlc_dti_tb
.
hdlcfg.TestBenchName = "mlhdlc_dti_tb";
Set the target language to SystemVerilog.
hdlcfg.TargetLanguage = "SystemVerilog";
Generate HDL code from your MATLAB design. In this example, the MATLAB design function name is mlhdlc_dti
.
codegen -config hdlcfg mlhdlc_dti
Generate Cosim and FIL Test Benches
Create a coder.FixptConfig
object that has default settings and
provide a test bench name.
fixptcfg = coder.config("fixpt"); fixptcfg.TestBenchName = "mlhdlc_sfir_tb";
Create a coder.HdlConfig
object that has default settings and set
enable rate.
hdlcfg = coder.config("hdl"); % Create a default "hdl" config hdlcfg.EnableRate = "DUTBaseRate";
Instruct MATLAB to generate a cosim test bench and a FIL test bench. Specify an FPGA board name.
hdlcfg.GenerateCosimTestBench = true;
hdlcfg.FILBoardName = "Xilinx Virtex-5 XUPV5-LX110T development board";
hdlcfg.GenerateFILTestBench = true;
Perform code generation, Cosim test bench generation, and FIL test bench generation.
codegen -float2fixed fixptcfg -config hdlcfg mlhdlc_sfir
Alternatives
You can also generate HDL code from MATLAB code using the HDL Workflow Advisor. For more information, see Basic HDL Code Generation and FPGA Synthesis from MATLAB.
Version History
Introduced in R2014b
See Also
Functions
Classes
Properties
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