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coder.HdlConfig

HDL codegen configuration object

Description

A coder.HdlConfig object contains the configuration parameters that the HDL codegen function requires to generate HDL code. To pass this object to the codegen function, use the -config option.

Creation

Description

example

hdlcfg = coder.config("hdl") creates a coder.HdlConfig object for HDL code generation.

Properties

expand all

General

HDL coding standard to follow when generating code, specified as a character vector or string array. Generates a compliance report showing errors, warnings, and messages.

Example: 'Industry' "Industry"

Data Types: char | string

HDL coding standard rules and report customizations, specified by using HDL Coding Standard Customization Properties. For more information, see HDL Coding Standard Customization Properties. If you want to customize the coding standard rules and report, you must set HDLCodingStandard to "Industry".

Target language of the generated code, specified as a character vector or string array.

Example: 'Verilog' "Verilog"

Data Types: char | string

Test bench function name, specified as a character vector or string array. You must specify a test bench.

Data Types: char | string

Workflow

Option to generate a cosimulation test bench, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

Option to generate a FIL test bench, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

Option to generate an HDL test bench, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

Option to simulate a generated cosimulation test bench, specified as a numeric or logical 1 (true) or 0 (false). This option is ignored if GenerateCosimTestBench is false.

Data Types: logical

Option to simulate a generated cosimulation test bench, specified as a numeric or logical 1 (true) or 0 (false). This option is ignored if GenerateCosimTestBench is false.

Data Types: logical

Option to simulate generated code, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

Option to synthesize generated code, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

SystemC test bench function name, specified as a character vector or string array. Specify the test bench for SystemC code generation.

Example: 'Test bench with random input stimulus'

Data Types: char | string

Target Tool Selection

Time (in clock cycles) between deassertion of reset and assertion of clock enable.

Data Types: int32

The number of nanoseconds the clock is high.

Data Types: int32

The number of nanoseconds the clock is low.

Data Types: int32

The hold time for input signals and forced reset signals, specified in nanoseconds.

Data Types: int32

Option to log and plot outputs of the reference design function and HDL simulator, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

Specify the time (in clock cycles) between assertion and deassertion of reset.

Data Types: int32

HDL simulator run mode during simulation, specified as a character vector or string array. When in Batch mode, you do not see the HDL simulator UI. The HDL simulator shuts down after simulation.

Example: 'GUI' "GUI"

Data Types: char | string

HDL simulator for the generated cosim test bench, specified as a character vector or string array.

Example: 'Incisive'"Incisive"

Data Types: char | string

List of additional source files to include, specified as a character vector or string array. Separate file names by using a semicolon (;).

Data Types: char | string

IP address of the FPGA board, specified as a character vector or string array. You must enter a valid IP address.

Data Types: char | string

MAC address of the FPGA board, specified as a character vector or string array. You must enter a valid MAC address.

Data Types: char | string

FPGA board name, specified as a character vector or string array. You must override the default value and specify a valid board name.

Data Types: char | string

Option to log and plot outputs of the reference design function and FPGA, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

Simulation tool name, specified as a character vector or string array.

Example: 'ISIM' "ISIM"

Data Types: char | string

Synthesis tool name, specified as a character vector or string array.

Example: 'Xilinx Vivado' "Xilinx Vivado"

Data Types: char | string

Synthesis target chip family name, specified as a character vector or string array.

Data Types: char | string

Synthesis target device name, specified as a character vector or string array.

Data Types: char | string

Synthesis target package name, specified as a character vector or string array.

Data Types: char | string

Synthesis target speed, specified as a character vector or string array.

Data Types: char | string

Specify the target frequency, in MHz, of the clock wired to the clock input of the generated HDL design. This frequency is the same as the output clock frequency of the clock module. Adaptive pipelining takes into account the target frequency that you set to improve the frequency of your design.

Data Types: double

Code Style

Option to initialize block RAM to 0 for simulation, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

Option to include inline configurations in generated VHDL code, specified as a numeric or logical 1 (true) or 0 (false).

When true, include VHDL configurations in files that instantiate a component.

When false, suppress the generation of configurations and require user-supplied external configurations. Set to false if you are creating your own VHDL configuration files.

Data Types: logical

Postfix to append to the design name to form the name of the timing controller, specified as a character vector or string array.

Data Types: char | string

Target library name for generated VHDL code, specified as a character vector or string array.

Data Types: char | string

Clocks

Active clock edge, specified as a character vector or string array.

Example: 'Rising' "Rising"

Data Types: char | string

Oversampling factor, specified as an integer greater than or equal to 1. Specify the frequency of global oversampling clock as a multiple of the design base clock rate.

Data Types: int32

Timing controller architecture, specified as a character vector or string array.

TimingControllerArch ValueDescription

default

Do not generate a reset for the timing controller.

resettable

Generate a reset for the timing controller.

Example: 'resettable' "resettable"

Data Types: char | string

Ports

Specify the maximum number of I/O pins for your target FPGA. If the DUT pin count in the generated code exceeds the maximum number of I/O pins set by this parameter, HDL Coder™ generates a warning in the HDL Conformance Report.

Data Types: int32

Optimizations

Option to insert adaptive pipeline registers in your design, specified as a numeric or logical 1 (true) or 0 (false). Enable adaptive pipelining to insert pipeline registers to the blocks in your design, reduce the area usage, and maximize the achievable clock frequency on the target FPGA device.

When you specify this parameter, specify the Synthesis Tool in the Select Code Generation Target task. If your design has multipliers, specify the Synthesis Tool and the Target Frequency (MHz) for adaptive pipeline insertion.

Data Types: logical

Minimum bit width for shared adders, specified as a positive integer.

If ShareAdders is true and ResourceSharing is greater than 1, share adders only if adder bit width is greater than or equal to AdderSharingMinimumBitwidth.

Data Types: int32

Option to use dataflow representation for MATLAB functions, specified as a numeric or logical 1 (true) or 0 (false). Transform the control flow algorithm of the MATLAB code inside a MATLAB function to a dataflow representation. Set this property to true for optimizations and options that use dataflow representation, such as frame-to-sample conversion and native floating-point optimizations.

If you set both AggressiveDataflowConversion and GenerateMLFcnBlock to true, you can generate a functionally equivalent Simulink® model of your MATLAB function design that contains Simulink blocks, which is comparable to designing the algorithm with Simulink.

Data Types: logical

Option to balance clock-rate pipelined DUT output ports, specified as a numeric or logical 1 (true) or 0 (false). Synchronize the DUT outputs while satisfying the highest-latency requirements of the outputs. Apply this option when interfacing your logic with a valid signal interface to align the output of the logic path and valid signal path.

Data Types: logical

Option to allow clock-rate pipelining of DUT output ports, specified as a numeric or logical 1 (true) or 0 (false). Set this property to true to produce the DUT outputs as soon as possible by passing the outputs from the DUT at the clock rate rather than the data rate.

Data Types: logical

Option to insert pipeline registers at the clock rate, specified as a numeric or logical 1 (true) or 0 (false). Use clock-rate pipelining to insert pipeline registers at a clock rate that is faster than the data rate. This optimization improves the clock frequency and reduces the area usage without introducing additional latency. Clock-rate pipelining does not affect existing design delays in your design.

Data Types: logical

Option to distribute pipeline registers, specified as a numeric or logical 1 (true) or 0 (false). When enabled, HDL Coder moves registers within your design to reduce the critical path.

Data Types: logical

Priority for distributed pipelining algorithm, specified as a character vector or string array.

DistributedPipeliningPriority ValueDescription
NumericalIntegrity (default)

Prioritize numerical integrity when distributing pipeline registers.

This option uses a conservative retiming algorithm that does not move registers across a component if the functional equivalence to the original design is unknown.

Performance

Prioritize performance over numerical integrity.

Use this option if your design requires a higher clock frequency and the MATLAB behavior does not need to strictly match the generated code behavior.

This option uses a more aggressive retiming algorithm that moves registers across a component even if the modified design’s functional equivalence to the original design is unknown.

Example: 'NumericalIntegrity' "NumericalIntegrity"

Data Types: char | string

Specify the number of input pipeline register stages. When DistributedPipelining is enabled, these registers can be distributed through the design.

Data Types: int32

Loop optimization in generated code, specified as a character vector or string array. See Optimize MATLAB Loops.

LoopOptimization ValueDescription
LoopNoneDo not optimize loops in generated code.
StreamLoopsStream loops.
UnrollLoopsUnroll loops.

Example: 'StreamLoops' "StreamLoops"

Data Types: char | string

Option to omit generation of clock enable logic, specified as a numeric or logical 1 (true) or 0 (false).

When false (default), generate clock enable logic.

When true, omit generation of clock enable logic wherever possible.

Data Types: logical

Specify maximum input bit width for hardware multipliers. If a multiplier input bit width is greater than this threshold, HDL Coder splits the multiplier into smaller multipliers.

To improve your hardware mapping results, set this threshold to the input bit width of the digital signal processor (DSP) or multiplier hardware on your target device.

Data Types: int32

Minimum bit width for shared multipliers, specified as a positive integer.

If ShareMultipliers is true and ResourceSharing is greater than 1, share multipliers only if multiplier bit width is greater than or equal to MultiplierSharingMinimumBitwidth.

Data Types: int32

Specify the number of output pipeline register stages. When DistributedPipelining is enabled, these registers can be distributed through the design.

Data Types: int32

Prevent distributed pipelining from moving design delays or allow distributed pipelining to move design delays, specified as a numeric or logical 1 (true) or 0 (false).

Persistent variables and dsp.Delay System objects are design delays.

Data Types: logical

Option to insert a pipeline register at each DUT input, specified as a numeric or logical 1 (true) or 0 (false). Distributed pipelining does not move these registers.

Data Types: logical

Option to insert a register at each DUT output, specified as a numeric or logical 1 (true) or 0 (false). Distributed pipelining does not move these registers.

Data Types: logical

Option to share adders, specified as a numeric or logical 1 (true) or 0 (false). If true, share adders when ResourceSharing is greater than 1 and adder bit width is greater than or equal to AdderSharingMinimumBitwidth.

Data Types: logical

Option to share multipliers, specified as a numeric or logical 1 (true) or 0 (false). If true, share multipliers when ResourceSharing is greater than 1 and multiplier bit width is greater than or equal to MultiplierSharingMinimumBitwidth.

Data Types: logical

Floating Point

Floating-point library name, specified as a character vector or string array.

Example: 'NativeFloatingPoint'

Data Types: char | string

Floating point target configuration when using native floating point for HDL code generation, specified as an hdlcoder.FloatingPointTargetConfig object. To configure the floating point target, see hdlcoder.FloatingPointTargetConfig. To generate HDL code from a MATLAB function, you can only set the native floating point properties HandleDenormals, LatencyStategy, and MantissaMultiplyStrategy in the hdlcoder.FloatingPointTargetConfig class.

Example: hdlcfg.FloatingPointTargetConfiguration = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT'), where hdlcfg is a coder.HdlConfig object. See createFloatingPointTargetConfig.

Data Types: hdlcoder.FloatingPointTargetConfig

Advanced Coding

Option to generate a Simulink model from your MATLAB function, specified as a numeric or logical 1 (true) or 0 (false). You must have a Simulink license.

If you set AggressiveDataflowConversion to false, this parameter generates a MATLAB Function block to use in a Simulink model.

If you set AggressiveDataflowConversion to true, this parameter generates a functionally equivalent Simulink model of your MATLAB function design that contains Simulink blocks that perform the algorithm designed in your MATLAB function. This model is similar to a generated model in the Simulink-to-HDL workflow.

Data Types: logical

Option to generate instantiable HDL code modules from functions, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

Check for reals in the generated HDL code, specified as a character vector or string array.

ValueDescription
NoneDo not check for reals in the generated HDL code.
WarningChecks and warns of presence of real data types in the generated HDL code. Real data types in the generated HDL code are not synthesizable on target FPGA devices.
ErrorChecks and generates an error if the generated HDL code uses real data types. If you are generating code for simulation purposes and not for synthesizing your design, you can change this setting to Warning or None. To generate synthesizable HDL code, set the Floating Point IP Library to Native Floating Point.

Example: 'None' "None"

Data Types: char | string

Test Bench

Maximum number of simulation iterations during test bench generation. This property affects only test bench generation, not simulation during fixed-point conversion. When the value is -1 (default), no maximum number of simulation iterations is set.

Data Types: int32

Option to create and use data files for reading and writing test bench input and output data, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

Lint Script

If you set HDLLintTool to Custom, you must use %s as a placeholder for the HDL file name in the generated Tcl script. Specify HDLLintCmd as a string array or character vector by using this format:

custom_lint_tool_command -option1 -option2 %s

Data Types: char | string

HDL lint script initialization name, specified as a character vector or string array.

Data Types: char | string

HDL lint script termination name, specified as a character vector or string array.

Data Types: char | string

HDL lint tool script to generate, specified as a character vector or string array.

Example: 'SpyGlass' "SpyGlass"

Data Types: char | string

Frame to Sample Conversion

Option to enable frame-to-sample conversion, specified as a numeric or logical 1 (true) or 0 (false). If your MATLAB function is not synthesizable because it requires a large amount of I/O, this optimization can reduce the I/O in the design and generate synthesizable HDL code. The frame-to-sample conversion converts matrix inputs to smaller samples by streaming the input signal for HDL code generation to reduce the I/O that handles a large input signal. For more information, see HDL Code Generation from Frame-Based Algorithms.

To enable this parameter, set AggressiveDataflowConversion to true.

Data Types: logical

Register size of generated input FIFOs, specified as an integer greater than or equal to 4. Use this parameter to specify the register size of the generated input FIFOs around the streaming matrix partitions. The frame-to-sample conversion generates an input FIFO for every input to the MATLAB function that has a sampled-based input signal.

To enable this parameter, set FrameToSampleConversion to true.

Data Types: int32

Register size of the generated output FIFOs, specified as an integer greater than or equal to 4. Use this parameter to specify the register size of the generated output FIFOs around the streaming matrix partitions. The frame-to-sample conversion generates an output FIFO for every output of the MATLAB function that has a sampled-based output signal.

To enable this parameter, set FrameToSampleConversion to true.

Data Types: int32

Samples per cycle, specified as an integer greater than or equal to 1. Use this parameter to specify the size of the signals after the frame-to-sample conversion streams them. The streamed input signal is either a scalar (one sample per cycle) or 1-D vectors with N elements (N samples per cycle).

To enable this parameter, set FrameToSampleConversion to true.

Data Types: int32

Examples

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Create a coder.HdlConfig object hdlcfg.

hdlcfg = coder.config("hdl"); % Create a default "hdl" config

Set the test bench name. In this example, the test bench function name is mlhdlc_dti_tb.

hdlcfg.TestBenchName = "mlhdlc_dti_tb";

Set the target language to Verilog®.

hdlcfg.TargetLanguage = "Verilog";

Generate HDL code from your MATLAB design. In this example, the MATLAB design function name is mlhdlc_dti.

codegen -config hdlcfg mlhdlc_dti

Create a coder.FixptConfig object that has default settings and provide a test bench name.

fixptcfg = coder.config("fixpt"); 
fixptcfg.TestBenchName = "mlhdlc_sfir_tb";

Create a coder.HdlConfig object that has default settings and set enable rate.

hdlcfg = coder.config("hdl"); % Create a default "hdl" config
hdlcfg.EnableRate = "DUTBaseRate";

Instruct MATLAB to generate a cosim test bench and a FIL test bench. Specify an FPGA board name.

hdlcfg.GenerateCosimTestBench = true;
hdlcfg.FILBoardName = "Xilinx Virtex-5 XUPV5-LX110T development board";
hdlcfg.GenerateFILTestBench = true;

Perform code generation, Cosim test bench generation, and FIL test bench generation.

codegen -float2fixed fixptcfg -config hdlcfg mlhdlc_sfir

Alternatives

You can also generate HDL code from MATLAB code using the HDL Workflow Advisor. For more information, see Basic HDL Code Generation and FPGA Synthesis from MATLAB.

Version History

Introduced in R2014b