Generate and Deploy IP Core
R2026bAn IP core is a portable and reusable HDL component that implements a specific function, typically an algorithm. An IP core consists of HDL code generated for your algorithm, packaged with IP core definition files, a C header file that contains the register address map, and an IP core report.
Using HDL Coder™, you can generate an IP core from your MATLAB® function or Simulink® model. The generated IP core can be manually integrated into an existing system, or deployed automatically with a reference design. For an example of manual integration of a generated IP core, see Generate Board-Independent HDL IP Core for Xilinx Platforms.
To deploy your IP core automatically use a reference design, which defines how the generated IP core integrates into a complete system. HDL Coder provides reference designs for many common hardware platforms, and applications. You can also author your own custom reference design. See Deploy IP Core on Custom Hardware.
If no pre-authored reference design exists for your hardware platform, HDL Coder can automatically generate one for you. By selecting
Auto-generated for your reference design, HDL Coder builds a complete, deployable system that includes your generated IP
core. For more information, see Deploy IP Core With Auto-Generated Reference Design.
For more details on the workflow, see Targeting FPGA and SoC Hardware Overview.
Classes
hdlcoder.WorkflowConfig | Configure HDL code generation and deployment workflows |
Topics
IP Core Generation
- Custom IP Core Generation
Generate a custom IP core from a model or algorithm using the HDL Workflow Advisor. - Custom IP Core Report
You generate an HTML custom IP core report by default when you generate a custom IP core. - Generate Board-Independent HDL IP Core from Simulink Model
When you open the HDL Workflow Advisor and run theIP Core Generationworkflow for your Simulink model, you can specify a generic Xilinx® platform, a generic Intel® platform, generic Microchip platform or generic platform. - Generate Board-Independent IP Core from MATLAB Algorithm
Board-independent IP core generation from MATLAB. - Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces
Learn how you can map your DUT ports to multiple AXI4-Stream, AXI4-Stream Video, and AXI4 Master interfaces. - IP Core Reset Interface
Learn how HDL Coder automatically inserts logic to synchronize global reset signal to IP core clock domain. - IP Core Clock Interface
Configure clock inputs for generated IP cores. - IP Core Generation Workflow for Standalone FPGA Devices
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design. - Deploy IP Core With Auto-Generated Reference Design
Generate and deploy an IP core to an AMD SoC board without selecting or authoring a pre-existing reference design. (Since R2026b)
AMD SoC Reference Designs
- Default System Reference Design for AMD FPGA Board (SoC Blockset)
Learn about the default system reference design for AMD FPGA board and using the reference design. - Default System Reference Design for AMD SoC Devices (SoC Blockset)
Learn about how to use Default system reference design and its requirements. - Default Video System Reference Design (SoC Blockset)
Learn about the default video system reference design and its requirements. - Reference Designs for RFSoC Devices (SoC Blockset)
Learn about how to use RFSoC reference designs and their requirements.
Intel SoC Reference Designs
- Default System Reference Design for Altera SoC Devices
Learn about the default system reference design and using the reference design for Altera SoC Devices. - Default System with External DDR4 Memory Access Reference Design
Learn about the default system with external DDR3 memory access reference design and its requirements.
Microchip SoC Reference Designs
- Default System Reference Design
Learn about the default system reference design and using the reference design.
Reference Design Integration
- IP Caching for Faster Reference Design Synthesis
Use IP caching to speed up reference design synthesis time by using an out-of-context workflow. - Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows
Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.
Featured Examples
Generate IP Core from Multirate Model
Learn various example designs that use multiple sample rates with IP Core Generation workflow.
Generate IP Core with Multiple AXI4-Stream Channels
Model an audio system with multiple AXI4-Stream channels and deploy it on a ZedBoard™ by using an audio reference design.
Integrate HDL IP Core with Versal AI Engine
Model, partition, and deploy a design that leverages the processor, FPGA, and AI Engines on a Versal device.
Getting Started with Targeting Xilinx Versal Adaptive SoC Platform
Use HDL Coder™ and the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Versal® Adaptive SoC platform.
