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Test design in hardware (requires HDL Verifier™)

When you generate HDL code in HDL Workflow Advisor, you can load the generated code into an FPGA board. You can optionally generate a Simulink® model that includes an FPGA-in-the-Loop block that communicates with your HDL design running on the FPGA board. The model also includes your original Simulink stimulus generation, behavioral model, and blocks that display or analyze output data. The model compares the output of the FPGA-in-the-Loop block against the output of the source subsystem.

To use this feature, you must install the HDL Verifier Support Package for Xilinx® or Altera® FPGA boards. See HDL Verifier Supported Hardware (HDL Verifier).


hdlcoder.WorkflowConfigConfigure HDL code generation and deployment workflows


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