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How to integrate with Verilog Code Generator with custome approach instead of Simulink?
web(fullfile(docroot, 'hdlcoder/gs/generate-hdl-code-from-matlab-code-using-the-command-line-interface.html')) This product hel...

fast 6 Jahre vor | 0

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How to integrate with Verilog Code Generator with custome approach instead of Simulink?
Here are some links that can help in describing the workflow to translate MATLAB to Verilog. Please note you need to follow best...

fast 6 Jahre vor | 0

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fixdt in simulink and fixed-point percision in system generator is equal ???
This should help answer the question on proper use of Xilinx System Generator and HDL Coder in an integrated workflow. https://...

fast 6 Jahre vor | 0

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HDL generation from inside a (library) linked subsystem
HDL code generation from reference subsystems is now supported in HDL Coder.

fast 6 Jahre vor | 0

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How to remove errors of Verify Fixed Point Design step of HDL Coder?
Fixed-point conversion is an assisted process. Automated conversion of fixed-point can fail if best practices of conversion are ...

fast 6 Jahre vor | 0

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how to use an external memory(ddr2, dpram) in HDL coder by matlab??
Performing Large Matrix Operation on FPGA using External Memory web(fullfile(docroot, 'hdlcoder/ug/performing-large-matrix-oper...

fast 6 Jahre vor | 0

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how does loop unroll work in hdl coder?
These HDL Coder documentation files should explain the behavior. https://www.mathworks.com/help/hdlcoder/ref/coder.hdl.loopspec...

fast 6 Jahre vor | 0

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How to solve "unsupported unbounded loop structure" error when generate hdl code from stateflow
The model has only dead logic. Please share updated model.

fast 6 Jahre vor | 0

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How to implement a 3D Lookup Table that can be converted with HDL Coder?
Can you consider the following modeling workaround until 3D LUT table support is available in HDL Coder?

fast 6 Jahre vor | 0

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How to implement a 3D Lookup Table that can be converted with HDL Coder?
3D LUT support is on the HDL Coder near term product roadmap and will be available in an upcoming release. In the interim we ca...

fast 6 Jahre vor | 0

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HDL Coder failing for single-precision
Thank you for reporting this error. This is unexpected. Can you share a reproduction model? It will help verify this issue is ...

fast 6 Jahre vor | 0

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Error in HDL Coder- Fixed point conversion "MATLAB expression 'r' is not of the correct class: expected 'double', found 'sym'."
You may want to check how to code this algorithm to be compatible with HDL Coder and FPGA Modeling Guidelines. There are some go...

fast 6 Jahre vor | 0

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is modelsim 10.7 is compitable with hdl verifier 2020a?
https://www.mathworks.com/help/hdlverifier/gs/supported-eda-tools.html Please check Mentor Graphics Questa and ModelSim Usage R...

fast 6 Jahre vor | 0

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HDL Coder RAM mapping failed
HDL Coder would need input types to infer the intermediate and output types. Please specify in = <sample value>; % define in...

fast 6 Jahre vor | 0

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How to resolve the exceed of maximum supported wordlength of 128 bits in hdlcoder?
HDL Coder supports various data types for synthesis. If you need high dynamic range in computation you need to use native floati...

fast 6 Jahre vor | 0

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problem generating hdl ip core of statflow using hdl workflow advisor: can't run the 1.2 task Set Target Reference Design
Unfortunately the attached model does not compile. Can you send updated instructions? === Update Diagram (Elapsed: 0.522 sec) =...

fast 6 Jahre vor | 0

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xmakefilesetup configuration for Xilinx software
HDLCoder works in conjuction with System Generator. See example here. https://www.mathworks.com/help/hdlcoder/examples/using-xi...

fast 6 Jahre vor | 0

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Eliminating algebraic loops with the Induction motor simulation
For HDL code generation the model first needs to be discretized (use z^-1 blocks). Attached is an example model with flux equat...

fast 6 Jahre vor | 0

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Why does Image Filter does not produce valid output when using certain image dimension?
Can you share a sample model that reproduces the issue? Thanks This is another example shows how to design a hardware-targeted ...

fast 6 Jahre vor | 1

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error while programming hardware :device arm dap_1 is not programmable
Per release notes this feature is available in R2020a release. https://www.mathworks.com/help/hdlverifier/release-notes.html ...

fast 6 Jahre vor | 0

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How to use the fixed-point designer properly - several issues.
Sure. Could you share sample models?

fast 6 Jahre vor | 0

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How to use the fixed-point designer properly - several issues.
This is a good Fixed-point resource and a HDL Coder primer on how to handle fixed-point challenges for ASIC/FPGA targeting. htt...

fast 6 Jahre vor | 0

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hdl coder work flow adviser block compability error
HDLCoder only supports binary-point scaling. The product currently does not support slope/bias scaling. You need to choose fixe...

fast 6 Jahre vor | 1

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Capture I2S data from FPGA board to MATLAB or Simulink
This example shows how to build a reference design to run an audio algorithm and access audio input and output on ZYBO board. ...

fast 6 Jahre vor | 0

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Capture I2S data from FPGA board to MATLAB or Simulink
Audio System on a Zynq Board The example shows how to build a reference design to run an audio algorithm and access audio input...

fast 6 Jahre vor | 0

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Are there enough resources in a Kintex7 160T for my Simscape Electrical model ?
Can you share a mat file with A,B,C,D,F0,Y0 values shown above? It depends if the matrix is largely sparse or has all non-zero v...

fast 6 Jahre vor | 0

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hdlsetuptoolpath miss (not exist) FPGA, Xilinx, HDL Coder,
There seems to be a problem with HDLCoder product installation. Reinstalling the product and checking for valid license would he...

fast 6 Jahre vor | 0

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How to control HDL QPSK Modem with Analog Devices No-OS Software
Analog Devices Engineer Zone - have a forum for no-OS drivers at https://ez.analog.com/microcontroller-no-os-drivers/. ADI’s T...

fast 6 Jahre vor | 0

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HDL Coder Flatten Hierachy does not work with masked library block
Will you be able to provide a model with reproduction steps? I suspect this is related to failure to do delay balancing due to ...

fast 6 Jahre vor | 0

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Wrap Xilinx IP in Simulink black box
>> I am asking how to wrap my HDL code in a block for use in Simulink Hi Talon, Have you checked this feature which clearly de...

fast 6 Jahre vor | 0