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Adaptive pipelining design cannot insert the required number of registers in a feedback loop with integral modules
What version of MATLAB are you using? Can you please share your model? Have you tried using Oversampling factor (>1) to allocat...

2 Monate vor | 0

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Failed Generated HDL code, testbench.
The model on the left has root ports; no stimulus/source blocks in the Simulink. The model on the right has valid sources/...

3 Monate vor | 0

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Examples of Simulink models of spacecraft subsystems controlled by FPGA algorithms
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-referenc...

3 Monate vor | 1

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Not able to Build FPGA BitStream for Simscape example model Half Wave Rectifier
Can you reach out to tech support? I am not sure if this could be Vivado version related issue.

3 Monate vor | 0

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Delay balancing error while using HDL coder
Hi Sanil, would you be able to share your model? Do not hesitate to reach to technical support and we can help further assist y...

3 Monate vor | 0

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Not able to Build FPGA BitStream for Simscape example model Half Wave Rectifier
https://www.mathworks.com/help/hdlcoder/ug/simscape-hil-speedgoat-fpga-io-modules.html What version of synthesis tools AMD/Xi...

3 Monate vor | 0

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How to work with arrays in HDL Coder?
See the attached sample code that demonstorates (line 15, 16) on how create large arrays. I am assuming you are using...

3 Monate vor | 0

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Why I can only choose Xilinx Vivado as the Synthesis tool?
Can you tell us what version of MATLAB are you using? Intel/Altera is supported. You need to have the right support package ins...

3 Monate vor | 0

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How to give random inputs for my simulink design?
You have to wrap the imported Simulink model from HDL Code into a subsystem. Add sources (constants, toworkspace blocks...) an...

3 Monate vor | 0

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Convert Simulink to m file
Correction in the above thread / Accepted Ansswer. Simulink Coder and embedded Coder products support C, C++ code generation...

3 Monate vor | 0

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FPGA Turnkey doesn't update Xilinx Vivado as synthesis tool even after setting tool path
Turnkey workflows are deprecated https://www.mathworks.com/products/hdl-coder.html To target FPGA and SoC devices, use the IP...

3 Monate vor | 0

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MATLAB Function always infers outputs as doubles
It would be hard to reproduce with the partial information above. Sharing a sample MATLAB function supported syntax for HDL cod...

3 Monate vor | 0

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HOW TO: Object detection using automotive RADAR
You should explore HDL Coder based examples in these two products Deep Learning HDL Toolbox: https://www.mathworks.com/help/dee...

3 Monate vor | 0

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Cannot write to AXI-Lite registers [HDL coder, PYNQ, HDL Vision toolbox]
For sobel filter examples using HDL Coder from Simulink consider reviewing these examples. (sampleIn and sampleOut DUT) https:...

3 Monate vor | 0

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I am trying to use "Deploy Neural Network Regression Model to FPGA/ASIC Platform" example
https://www.mathworks.com/matlabcentral/answers/2102651-i-am-trying-to-use-deploy-neural-network-regression-model-to-fpga-asic-p...

4 Monate vor | 0

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How can HDL Code Generation for a full system be performed with System Composer Model that contains multiple Simulink models?
Hi Brad, can you create a support request to help further address this issue? We can followup offline on how to connect System ...

4 Monate vor | 1

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Implementing logarithmic function via Simulink HDL Coder
Can you share a bit more about your application and requirements for log? These results can be generated based on your target...

4 Monate vor | 0

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Difference of sine waveform in simulink and real-time
You may find this workflow useful: https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-from-simscape-model.html >> whi...

4 Monate vor | 0

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Confused between Hardware to perform Inference
You can follow this example to see how to customize the generated DL Processor with HDL Coder. https://www.mathworks.com/help/d...

4 Monate vor | 1

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HDL Coder compatibility issue with Libero SoC 2023.2
It looks like you are using MATLAB R2023b and Libero 2023.2. Please confirm. As per HDL Coder supported versions, you need to...

5 Monate vor | 0

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Loop based error while performing HDL conversion using HDL workflow
Your MATLAB Coding style is incompatible with MATLAB to HDL workflow. Here are few general pointers while we respond to your spe...

5 Monate vor | 0

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Resources utilization for generated HDL code
Please find the attached slides that show how to generate the FPGA Synthesis report from a Simulink model using HDL Coder.

5 Monate vor | 0

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Resources utilization for generated HDL code
This is an estimation report from HDL Coder. >> makehdl('sfir_fixed/symmetric_fir') ### Working on the model sfir_fixe...

5 Monate vor | 0

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Dataflow Conversion Error when generating hdl code from simulink
This is an unexpected error and seems related to this bug report. https://www.mathworks.com/support/bugreports/3054173

5 Monate vor | 0

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Is there anyway to test custom IP cores on MATLAB/SIMULINK
You can make a DUT with Simulink subsystems and combine them with your custom IP using Black box interface and the combined IP c...

5 Monate vor | 0

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IP core generation for built-in Simulink model
Unfortunately we do not have your contact in our tech support database. Can you reach out to our support team via email to suppo...

5 Monate vor | 0

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is there a way to define 'fixdt' in a Matlab script and use this variable in a Simulink User-Defined Function?
Can you share a bit more details of this usecase? A sample model would be helpful. Are you using this in the context of a MATL...

5 Monate vor | 0

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Trouble with Vitis Model Composer 2023.2! MATLAB R2021b crashes when I want to open the Model Composer Hub component.
This might be related to a known MATLAB issue: https://www.mathworks.com/matlabcentral/answers/364551-why-is-matlab-unable-to...

6 Monate vor | 0

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IP core generation for built-in Simulink model
Please share your model if possible. I am attaching few sample design patterns that show how to build HDL Coder compliant desi...

6 Monate vor | 0

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what is the difference between FPGA Turnkey and IP Core Generation?
Targeting FPGA & SoC Hardware with HDL Coder Workflow Design a system that you can deploy on hardware or a combination of h...

6 Monate vor | 1