Statistik
RANG
99.791
of 301.275
REPUTATION
0
ANTWORTZUSTIMMUNG
0.0%
ERHALTENE STIMMEN
0
RANG
of 21.216
REPUTATION
N/A
DURCHSCHNITTLICHE BEWERTUNG
0.00
BEITRÄGE
0 Dateien
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANG
of 173.777
BEITRÄGE
0 Probleme
0 Lösungen
PUNKTESTAND
0
ANZAHL DER ABZEICHEN
0
BEITRÄGE
0 Beiträge
BEITRÄGE
0 Öffentlich Kanäle
DURCHSCHNITTLICHE BEWERTUNG
BEITRÄGE
0 Discussions
DURCHSCHNITTLICHE ANZAHL DER LIKES
Feeds
Beantwortet
Unable to update models referenced by... Error
Hi I also faced the same problem. Solution is to remove the space in the folder name. For example if a model is saved in folder...
Unable to update models referenced by... Error
Hi I also faced the same problem. Solution is to remove the space in the folder name. For example if a model is saved in folder...
etwa ein Monat vor | 0
Frage
Referenced model output of three phase voltage and current are 65535
I had converted the matlab function block into referenced model for running in Processor-In-Loop (PIL) and I had kept the code i...
3 Monate vor | 1 Antwort | 0
1
AntwortBeantwortet
Autogenerated VHDL for FPGA - In - The Loop DUT I/O Issue "** HDL Parser Error: line XX: near "vector_of_std_logic_vector32", found unsupported data-type "vector_of_std_logic_vector32""
In HDL coder setting enable Scalarize ports. Steps for enabling Scalarize ports: HDL code --> Setting --> Configuration parame...
Autogenerated VHDL for FPGA - In - The Loop DUT I/O Issue "** HDL Parser Error: line XX: near "vector_of_std_logic_vector32", found unsupported data-type "vector_of_std_logic_vector32""
In HDL coder setting enable Scalarize ports. Steps for enabling Scalarize ports: HDL code --> Setting --> Configuration parame...
4 Monate vor | 0
Frage
sampling time mismatch in simulink and harware
i am having a simulink model in matlab which is running on sampling time of 5e-6 second now i want to run my matlab file in zedb...
4 Monate vor | 2 Antworten | 0

