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Last seen: 2 Tage vor | Aktiv seit 2024

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How to use the deep learning IP core generated by deep learning hdl toolbox
Hi, I have successfully generated a deep learning IP core and integrated it into the official reference design, where it wo...

23 Tage vor | 1 Antwort | 0

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How to register a reference design that contains block design, rtl, and xilinx IP core?
Hi, I’m trying to register my reference design in MATLAB, but the documentation only covers pure block-design flows. My projec...

etwa 2 Monate vor | 1 Antwort | 0

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Target platform 'DLXCKU5PE' is not supported for quantization.
Hi, DLXCKU5PE is my self-generated deep learning bitstream with the datatype of int8. When I want to validate the quantized...

3 Monate vor | 1 Antwort | 0

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How to generate ps ethernet axi manager for custom board?
Hi, I want to generate a ps ethernet axi manager to capture data from the DAC / PS DDR. However, the FPGA board manager can...

8 Monate vor | 1 Antwort | 1

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Deep Learning HDL TOOLBOX does not support PLEthernet?
Hello, I want to accelerate the data transmission between my pc and fpga. Does DEEP LEARNING HDL TOOLBOX support PLETH...

10 Monate vor | 1 Antwort | 0

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How does PC build connection with UDP AXI MANAGER?
Hi, This problem has been solved. I found an ip core that can convert gmii to rgmii interface. URL: FPGA以太网篇之GMII转RGMI...

10 Monate vor | 0

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How does PC build connection with UDP AXI MANAGER?
Hi, I want to use udp axi manager to accelerate the data transmission between my pc and FPGA. However, my FPGA does not hav...

10 Monate vor | 1 Antwort | 0

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Does AXI Manager support RGMII
Hello, I want to accelerate the data transmission between PC and FPGA, by replace JTAG by PLEthernet. However, my FPGA only...

10 Monate vor | 1 Antwort | 0

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What's the most suitable Vivado version for Matlab 2025a
Hello, I'm happy to hear that the Matlab 2025a has been released. I have an AMD Versal AI Edge evaluation board, and I want...

10 Monate vor | 1 Antwort | 0

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Beantwortet
ENCOUNTER ERROR while using the FPGA system_top.tcl
I found the dame solution, The problem is caused by this segment: The setup of the DDR4: # Create instance: ddr4_0, and ...

etwa ein Jahr vor | 0

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ENCOUNTER ERROR while using the FPGA system_top.tcl
Hi, I want to learn the reference design from the official given example: Deep Learning Processor IP Core Generation for Cu...

etwa ein Jahr vor | 1 Antwort | 0

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hW.deploy stuck after programming the bitstream
Hi, After successfully compiling the hardware, ### Allocating external memory buffers: offset_name ...

etwa ein Jahr vor | 1 Antwort | 0

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The FPGA resource estimation for device family 'Kintex Ultrascale+'
Hello, I create a FPGA board with the device family of 'Kintex Ultrascale+'. At the Step of fpga resource estimation...

etwa ein Jahr vor | 1 Antwort | 0

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fail to set the hPC.TargetPlatform
找到原因了，开发板注册文件与参考设计注册文件不能放在一个文件夹 Translation: Found the reason. The development board registration file and the reference desig...

etwa ein Jahr vor | 0

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fail to set the hPC.TargetPlatform
Hi, I followed the guide of the Deep Learning Processor IP Core Generation for Custom Board . At the Step set the impo...

etwa ein Jahr vor | 1 Antwort | 0

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Beantwortet
Could not find compatible AXI Manager IP
明白原因了，必须使用matlab专用的jtag2axi ip核，其路径为： % C:\Program Files\MATLAB\R2022a\toolbox\hdlverifier\supportpackages ... % \fpgadebu...

etwa ein Jahr vor | 0

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unable to find FTD2XX library path
Hi, When i use h=aximanager('AMD','JTAGCableType','FTDI'); in Ubuntu 20.04 LTS system. An error occurs...

etwa ein Jahr vor | 2 Antworten | 0

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Could not find compatible AXI Manager IP
Hi, I want to access to the DDR4 using jtag 2 axi manager, I have set a jtag 2 axi ip core in my block design: And if I ...

etwa ein Jahr vor | 1 Antwort | 0

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How to generate CUSTOM REFERENCEDESIGN for deep learning ip core?
您好，我想要将神经网络部署到我的FPGA上，但是我的FPGA并不是Matlab直接支持的，所以我在生成deep learning ip core的时候选择了‘Generic Deep Learning Processor’,我很疑惑的是这个IP...

etwa ein Jahr vor | 1 Antwort | 0

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fpga in loop tesy error fail to initialize the rtioStream library
The problem has been solved! Thanks to the help and the guidance! Two packages are needed to solve this question. 1.FTD2XX li...

etwa ein Jahr vor | 0

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fpga in loop tesy error fail to initialize the rtioStream library
When i create my custom fpga board, i meet with this error: Error:Failed to initialize the RTIOStream library. Failed to open ...

etwa ein Jahr vor | 1 Antwort | 0

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how to download the third party support package file "xilinx linux binaries"
Hello, I have tried several times to download the third party support package "xilinx linux binaries". download error, Can no...

etwa ein Jahr vor | 4 Antworten | 0

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How to add vivado to the matlab in ubuntu/linux system?
Hello, I install the matlab 2024b and vivado 2023.2 on the ubuntu 20.04. The command 'hdlsetuptoolpath' needs the fil...

etwa ein Jahr vor | 1 Antwort | 0

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what kind of basic FPGA system is needed for deep learning IP core generation?
I'm tring to deploy my deep learning network on FPGA. I need to create my FPGA evaluation board. Now, I have two questions. i...

etwa ein Jahr vor | 2 Antworten | 0

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