Statistik
RANG
296.406
of 300.779
REPUTATION
0
ANTWORTZUSTIMMUNG
50.0%
ERHALTENE STIMMEN
0
RANG
of 21.084
REPUTATION
N/A
DURCHSCHNITTLICHE BEWERTUNG
0.00
BEITRÄGE
0 Dateien
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANG
of 170.997
BEITRÄGE
0 Probleme
0 Lösungen
PUNKTESTAND
0
ANZAHL DER ABZEICHEN
0
BEITRÄGE
0 Beiträge
BEITRÄGE
0 Öffentlich Kanäle
DURCHSCHNITTLICHE BEWERTUNG
BEITRÄGE
0 Discussions
DURCHSCHNITTLICHE ANZAHL DER LIKES
Feeds
FPGA Data Capture in Custom Board
Is that a variable that should be declared within the plugin_rd() function? My HDL coder reference design uses a custom Qsys des...
18 Tage vor | 0
Frage
FPGA Data Capture in Custom Board
I have a custom cyclone v soc board. I'm trying to follow along with debug IP core using FPGA Data Capture. https://www.mathwork...
19 Tage vor | 3 Antworten | 0
3
AntwortenFrage
PMLSM Modeling cogging forces
Is there a way to modify the PMLSM Simscape block so that it accurately models cogging forces?
21 Tage vor | 1 Antwort | 0
1
AntwortFrage
FPGA in the loop Workflow
I need more help understanding the FPGA in the loop verification workflow. I have PMSM controller in Simulink that was converted...
26 Tage vor | 0 Antworten | 0
0
AntwortenFrage
Connect AXI4 Master to multiple slaves
I defined an AXI4 Master Interface using the addAXI4MasterInterface method in my plugin_rd file. I want the master interface to ...
etwa ein Monat vor | 1 Antwort | 0
1
AntwortFrage
HDL Coder Error when converting AXI4 interface with different data rates
I'm having trouble understanding this error from HDL coder: Failed All the DUT ports connecting to the "f2h_sdram0 Read" interf...
etwa 2 Monate vor | 1 Antwort | 0
1
AntwortFrage
AXI4 Master Read SDRAM
I'm using a Cyclone V SoC and in my reference design I have a FPGA to HPS SDRAM Interface enabled under the HPS. I'm expecting s...
3 Monate vor | 1 Antwort | 0
1
AntwortFrage
Unable to fit HDL coder design into FPGA
I'm having trouble getting the HDL IP core generated by the HDL coder to fit in the FPGA I'm targeting (Cyclone V). I'm using th...
4 Monate vor | 1 Antwort | 0
1
AntwortFrage
PMLSM Controller Over Active
I started with the three phase PMLSM example: https://www.mathworks.com/help/sps/ug/three-phase-pmlsm-drive.html . I modified th...
5 Monate vor | 1 Antwort | 0
1
AntwortFrage
Specify the Location of custom IP cores in HDL Coder
I was following along with the instructions here: https://www.mathworks.com/help/hdlcoder/ug/define-and-add-ip-respository-to-cu...
9 Monate vor | 1 Antwort | 0
1
AntwortFrage
HDL Coder with Custom IP Core
I was trying to add a custom IP core to my reference design and now when I run HDL workflow advisor using the hdl_led_blinking s...
9 Monate vor | 1 Antwort | 0
1
AntwortFrage
Cannot find header file in Simulink Coder
I'm using the C Function block in Simulink to import custom C code into my model. Most of the standard C libraries I include Sim...
10 Monate vor | 2 Antworten | 0
2
AntwortenFrage
Read AXI4 address locations from Simulink
How can I read a particular address location from the AXI4 interface within Simulink HDL coder? For example, if I have a referen...
10 Monate vor | 1 Antwort | 0
1
AntwortFrage
Build Linux Image for HDL Coder
I'm trying to follow along with the documentation here: https://www.mathworks.com/help/hdlcoder/ug/xilinx-zynq-linux-image-for-c...
10 Monate vor | 1 Antwort | 0
1
AntwortFrage
Use Conduit Interface in HDL Coder
If I have a reference design that includes an IP core with a Conduit interface, how can I reference these signals in HDL coder? ...
10 Monate vor | 0 Antworten | 0
0
AntwortenFrage
HDL Coder Support Package for Intel FPGA and SoC Devices Setup
I am trying to go through the hardware setup for the HDL Coder Support Package for Intel FPGA and SoC Devices. I get to the step...
11 Monate vor | 0 Antworten | 0
0
AntwortenFrage
Specify clock pins in HDL Reference Design
I was reading over how to register a custom reference design: https://www.mathworks.com/help/hdlcoder/ug/register-a-custom-refer...
11 Monate vor | 1 Antwort | 0
