Angela Cuadros Castiblanco

Last seen: 6 Tage vor | Aktiv seit 2023

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How to create this in Simulink? std_logic_vector16 vec[0:3]
Hello Cheri, If you're generating HDL code from a Simulink subsystem using makehdl, the behavior you're describing is already s...

7 Monate vor | 1

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Specify clock pins in HDL Reference Design
Hi John, The addClockInterface API in HDL Coder requires you to specify a connection point in your design. For instance, if you...

11 Monate vor | 1

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simulink ip core generation
Hello, To use the AXI4-Stream interface in the IP core generation workflow in HDL Coder, you can model your algorithm to operat...

mehr als ein Jahr vor | 0

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AXI-stream interface violates AXI-stream protocol
Hello Alexander, I'd like to provide some clarity on the protocol implementation within our IP core generation workflow. When m...

fast 2 Jahre vor | 0

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Setting Target interface fails in Debug Zynq design using HDL and Embedded coder example.
Hello Vishnu, The error message you're seeing typically appears when a reference design requires certain non-optional interfac...

etwa 2 Jahre vor | 1

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HDL Workflow Advisor - Step 3.2 - "Failed Index exceeds the number of array elements. Index must not exceed 2" in hdlturnkey.interface.ChannelBased/connectFrameInterfacePort
Hello, From your description it sounds like you are using the "legacy frame-based modeling" detailed in: https://www.mathwor...

mehr als 2 Jahre vor | 0

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