photo

JOAQUIN GARCIA ORDOÑEZ


Last seen: 8 Monate vor |  Aktiv seit 2020

Followers: 0   Following: 0

Statistik

  • First Review
  • Thankful Level 1

Abzeichen anzeigen

Feeds

Anzeigen nach

Frage


Processor and FPGA Synchronization in Coprocessing Mode
Hello everyone. I'm following this documentation to run an experiment that is hardware-in-the-loop: https://mathworks.com/help/...

etwa 3 Jahre vor | 1 Antwort | 0

1

Antwort

Frage


HDL Coder won't map LUT into BRAM
Hello everyone. I am trying to implement a machine learning algorithm into an FPGA using HDL Coder. I was recommended to use LU...

mehr als 3 Jahre vor | 1 Antwort | 0

1

Antwort

Frage


How can I modify mapping options in HDL Workflow Advisor in Simulink?
Hi everyone. I am trying to implement a design on a FPGA using Simulink's HDL Workflow Advisor. The block that I am trying to i...

mehr als 4 Jahre vor | 1 Antwort | 0

1

Antwort