Chandra Adusumalli

Last seen: 3 Monate vor | Aktiv seit 2021

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How to make a proper data transfer between FPGA and Processor?
Hi Seregi, You can refer below example for streaming data tarnsfer between hardware and software. Streaming Data from Hardware...

6 Monate vor | 0

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How are RFDC block and AXI4-Stream to Software block settings applied to the target board by SoC Builder?
Hi Sergei, The settings configured in the RFDC block are mapped to the corresponding parameters of the RF Data Converter IP ...

6 Monate vor | 2

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Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?
SoC Builder considers the hdl code generation settings in the FPGA model configuration. Please refer to the following link for m...

7 Monate vor | 1

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Beantwortet
Support for RFSoC 2x2 kit for academics
Hi Peter Hobden, You can use this RFSoC Template - MATLAB & Simulink (mathworks.com) RFSoC template from SoC Blockset to crea...

mehr als 3 Jahre vor | 0

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HDL System Blockset FPGA design generation Error
Hi Shady, Please use proper downsampler for data and use same rate trantition block for valid and ready signals in your design....

mehr als 3 Jahre vor | 1

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Having difficulty with examples using the socModelCreator to from the SoC Blockset
Hi Jim Esmond , You need to install 3rd party software tools after installing SoC Blockset supportpackage for Xilinx devices....

mehr als 3 Jahre vor | 0

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OFDM Transmit and Receive Using Xilinx RFSoC Device
Hi, Have you done Hardware setup after installing the supportpackages? If you have not done already and please follw this link ...

mehr als 4 Jahre vor | 0

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