QPSK Modulation Verilog Code generation error?

Hello

hope you are doing well.

i am using QPSK modulation IP and want to create Verilog code using that but it show me some error like mention in picture

Answer 1

[Bharath Venkataraman]

It appears that you need to covert the design to use fixed-point as well as set appropriate sample rates for your sources. Please take a look at this example to see how you can change your design.