Is it possible to generate DPI model of PLL Testbench block and use it inside SystemVerilog/UVM testbench?

I have an UVM testbench and I am trying to measure PLL performance like mean frequency error compared to target frequency, settling time and integrated phase noise. Currently I have SystemVerilog class to do it. This is a legacy class and seem to have bug.

Is it possible to generate DPI component for Mathworks PLL testbench and use it inside UVM testbench?

Answer 1

[Marc Erickson]

A very interesting idea! The SystemVerilog DPI component generation currently supports only Fixed Step solvers to allow easy integration into a digital HDL simulation context. PLL modeling, including the PLL Testbench block, uses continuous sample times and variable step sizes for efficient simulation. Trying to export such a modeling interface would require a very different integration context on the SystemVerilog side. If you have an AE working with you please reach out to share your use-cases to understand if there are any workarounds or incremental steps that can help you. Also, contacting customer support to raise an escalation with development will allow development to log and track the request.

[Gunjan Upadhyay]

Thank you, Marc for the explanation.