Error when parsing VHDL with moden commenting style.
1 Ansicht (letzte 30 Tage)
Ältere Kommentare anzeigen
MATLAB version: R2019a Update 6.
Hi All,
Not sure if this is owing to my using a slightly older version of Matlab, but there are errors when I try to import vhdl files into blackboxes in Simulink owing to the commenting style used. I recieve an error like the following with using the VHDL 2008 commenting standard (/* ... */):
- Error reported by S-function 'sysgen' in 'casper_counter/Black Box': The following error occurred with the casper_counter/Black Box block: Block initialization code, "common_counter.vhd", caused the MATLAB error: Error using xlbbCreateConfig Could not parse "/home/talon/Documents/CASPERWORK/casper_dspdevel/casper_counter/common_counter.vhd": Error: line 1:1 Syntax error, "/" encountered.
Will this be fixed in new versions?
Thank you.
Talon.
0 Kommentare
Antworten (0)
Siehe auch
Kategorien
Mehr zu HDL Verifier finden Sie in Help Center und File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!