Which versions of Xilinx Vivado are supported with which release of HDL Coder?

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I would like to use HDL Coder and its HDL Workflow Advisor to automate the programming of my Xilinx FPGA. For this, I need to install Xilinx Vivado Design Suite as synthesis tool. Could you tell me which versions of Xilinx Vivado are compatible with which releases of MATLAB/HDL Coder?

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MathWorks Support Team
MathWorks Support Team am 1 Mär. 2024
Bearbeitet: MathWorks Support Team am 1 Mär. 2024
Here is a list of MATLAB releases and the Xilinx Vivado versions that HDL Workflow Advisor has been tested against:
  • R2024a: Xilinx Vivado 2023.1
  • R2023b: Xilinx Vivado 2022.1
  • R2023a: Xilinx Vivado 2022.1
  • R2022b: Xilinx Vivado 2020.2
  • R2022a: Xilinx Vivado 2020.2
  • R2021b: Xilinx Vivado 2020.1
  • R2021a: Xilinx Vivado 2019.2
  • R2020b: Xilinx Vivado 2019.2
  • R2020a: Xilinx Vivado 2019.1
  • R2019b: Xilinx Vivado 2018.3
  • R2019a: Xilinx Vivado 2018.2
  • R2018b: Xilinx Vivado 2017.4
  • R2018a: Xilinx Vivado 2017.2
  • R2017b: Xilinx Vivado 2016.4
  • R2017a: Xilinx Vivado 2016.2
  • R2016b: Xilinx Vivado 2015.4
  • R2016a: Xilinx Vivado 2015.2
  • R2015b: Xilinx Vivado 2014.4
  • R2015a: Xilinx Vivado 2014.2
  • R2014b: Xilinx Vivado 2013.4
Important Notes:
(1) HDL Coder generated VHDL/Verilog code is Vivado version independent and works with any version of the Xilinx software. The above list refers to using HDL Workflow Advisor for integrated workflows such as IP core and bitstream generation. If you are interested in generating VHDL/Verilog code only, without invoking a synthesis tool, see the following post:https://www.mathworks.com/matlabcentral/answers/1643865-how-do-i-generate-code-only-with-hdl-coder
(2) For the Generic ASIC/FPGA workflow in HDL Workflow Advisor, note that the above list states the last supported Xilinx Vivado version for each release. For example, if you work with HDL Coder R2020a, you should be able to use HDL Workflow Advisor with Xilinx Vivado 2019.1 and all previously tested Xilinx Vivado versions, all the way back to 2013.4.
(3) For the IP Core Generation and Simulink Real-Time FPGA I/O workflow in HDL Workflow Advisor, it is recommended to use the exact Xilinx Vivado version that is stated in the list above for your release, or one of the exact version(s) that is supported by the reference design that you are using. You can see this information in HDL Workflow Advisor step 1.2. after selecting your desired reference design:
Learn More:
For more information regarding synthesis tool and device support by HDL Coder, see the "Supported Third-Party Tools and Hardware" documentation page:

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