HDL Coder Filter Latency

2 Ansichten (letzte 30 Tage)
Ewan Mackenzie
Ewan Mackenzie am 23 Mär. 2020
Kommentiert: Ewan Mackenzie am 27 Mär. 2020
Hi
Ive complied a fully paralell FIR filter using the FilterDesigner and HDL Coder and it reported the latency as 2. I am struggling to understand what the latency is exactly, is it the number of clocks required for a valid output? - 1 clock for multiplication and another for summing, but if so would the delay pipeline not also require a clock cycle?
-- -------------------------------
-- Filter Structure : Direct-Form FIR
-- Filter Length : 65
-- Stable : Yes
-- Linear Phase : Yes (Type 1)
-- Arithmetic : fixed
-- Numerator : s16,15 -> [-1 1)
-- Input : s16,15 -> [-1 1)
-- Filter Internals : Full Precision
-- Output : s33,30 -> [-4 4) (auto determined)
-- Product : s31,30 -> [-1 1) (auto determined)
-- Accumulator : s33,30 -> [-4 4) (auto determined)
-- Round Mode : No rounding
-- Overflow Mode : No overflow
-- -------------------------------------------------------------
Thanks in advance.

Akzeptierte Antwort

Aman Vyas
Aman Vyas am 27 Mär. 2020
Hi,
Latency is defined as the total number of clock cycles required in obtaining the output.
It will depend which path are you seeing for delay pipeline. If the path you are seeing for output that will require 2 cycles.
For more information read the following article:
Hope this helps !
  1 Kommentar
Ewan Mackenzie
Ewan Mackenzie am 27 Mär. 2020
Exactly what I was looking for, thank you

Melden Sie sich an, um zu kommentieren.

Weitere Antworten (0)

Kategorien

Mehr zu HDL Code Generation finden Sie in Help Center und File Exchange

Produkte

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by