How to speed up a Simulink simulation of slow mechanics requiring a fast clock?

What are the best methods to speed up a simulation that uses a 5Mhz clock but needs to simulate 2 sec of run-time?

I am running a brushless DC motor in a phase lock loop (DPLL) simulation and am concerened with estimating jitter. My actual system uses a 50MHz clock in a FPGA. I am simulating with a 5MHz clock because I want a resolution of at least 0.2us on jitter estimates.

I am using a combination of S-functions and sub-sytems. I am using a boolean pulse generator at 5Mhz as the clock. My motor model is continuous time. I only run S-functions if the clock transitions low to high. I only run the phase detector on the rising edge of the reference or feedback as sampled with the rising edge of the boolean clock. The compensation, a digital filter, is an S-block that is only run if the phase detector state changes. The effective sample rate is 360Hz.

Because it is a mechanical system I need to simulate about 2 seconds of time to gather lock and seettle.

Thanks,

Brian

[Brian Tremaine]

I put phase detector code in an S-function because I thought that would be faster than a sub-system. I guess thats a wrong assumption ;) I wrote the phase detector code with "if - else" structures paralleling closely the verilog code I used to implement it in an FPGA. If the boolean clock does not transition high the majority of the code in the 'update' is not executed.

Do you think execution would be faster if I 1) Generated a C compiled S-function or 2) Implement the phase detector using logic gates & counters in a sub-system ?

Thanks for your helpful advice,

Brian

Answer 1

[Bharath Venkataraman]

There are a wide variety of things you can do. The first thing to try is to run the model in Accelerator or Rapid Accelerator mode. You can also try to change the model to simulate frames rather than scalar values.

Here is a documentation page devoted to the topic.

[Brian Tremaine]

I put phase detector code in an S-function because I thought that would be faster than a sub-system. I guess thats a wrong assumption ;) I wrote the phase detector code with "if - else" structures paralleling closely the verilog code I used to implement it in an FPGA. If the boolean clock does not transition high the majority of the code in the 'update' is not executed.

Do you think execution would be faster if I 1) Generated a C compiled S-function or 2) Implement the phase detector using logic gates & counters in a sub-system ?

Thanks for your helpful advice,

Brian