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What values to use for minimum blancking for a pixel streaming interface

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Alla am 21 Mai 2019
Geschlossen: MATLAB Answer Bot am 20 Aug. 2021
I'm using the pixel streaming interface to analyse some HDL supported blocks, basically tying to get mroe details on timing and the number of clock cycles needed to produce an output, the goal is to get a detailed understanding that would allow me to actually put these as generic equations and attempt to estimate timing for larger inputs.
The block I'm testing now is the Image Filter block, timing and clock cycles are dependent on the values chosen for blanking, I'm unsure about those, is there a rule to pick the minimum values for blanking when you have a custom input? say I have a 4 by 4 input I'm feeding into the filter, what would be the minimum blanking value I'd need to produce a valid output? till now I've been just trying different values until I get valid results.
Any information on what happens inside the Image Filter block would be appreciated too, I'm assuming it used the cotnrol signal to buffer the valid pixels into FIFOs then pop out elements to produce a valid window which is multiplied and accumulated by the filter.

Antworten (1)

Bharath Venkataraman
Bharath Venkataraman am 21 Mai 2019
Typical video interfaces (240p and higher resolution) will have sufficient blanking, so one way to go is to pick blanking requirements from the closest resolution. Blanking intervals are listed in a table in the help page for the Frame To Pixels block.
For the Image Filter, a good back of the envelope calculation is to have the blanking twice the kernel size. based on the Image Filter block documentation, the blanking also needs to be greater than the latency of the block.
You can send the input and output signals of the Image Filter block to the Logic Analyzer to quickly determine the latency.
  8 Kommentare
Alla am 24 Mai 2019
Bearbeitet: Alla am 24 Mai 2019
Thank you for your help, what I mean by latency is simply exact timing, harware systems are deterministic, If I have a design that crries out 2D convolutions on an input I should know how many cycles it takes exctly for the input to be stored into line buffers or FIFOs and how many cycles it takes for it to be processed, multiplied and accumulated, granted this is usually done on the VHDL end of things using test benches but HDL coder presents a new model based design approach, so I was trying to figure that out from the model. so basically for thise 22 and 424 numbers I wated to know where they come each time.
Bharath Venkataraman
Bharath Venkataraman am 24 Mai 2019
In that case, I think it is best if you run the HDL code in the HDL simulator to see the latency. The line buffer code is in a separte entity so if you look at the vStart and processData coming out of the module in a waveform viewer, it's pretty easy to track down the latency.




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