Why can I not change the architecture of my subsystem to Black Box?
1 Ansicht (letzte 30 Tage)
Ältere Kommentare anzeigen
I am using R2018b. My end goal is to use FPGA in the Loop programming. I have verilog files that I want to include as a black box but I cannot change the architecture of my simulink subsystem to a blackbox.
0 Kommentare
Antworten (3)
Raghav Singhal
am 20 Feb. 2019
Please see this documentation page for details on generating a black box interface:
Antti Mattila
am 30 Dez. 2019
I seem to have the same problem. The "BlackBox" architecture option is not available for a subsystem. (I'm using 2018b also).
For some subsystem/refrenced models it is. This seems arbitrary.
0 Kommentare
Sina Aghli
am 18 Jan. 2020
I'm having the same issue(R2019a), has this feature been deprecated?
1 Kommentar
Sina Aghli
am 18 Jan. 2020
I create a HDL/Subsystem and then rightckick then HDL Code -> HDL Block Properties ...
then in "HDL properties::Subsystem" window under Implementation->Architecture, the only available option is "Module" and there is no blackbox option
Siehe auch
Kategorien
Mehr zu FPGA, ASIC, and SoC Development finden Sie in Help Center und File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!