When mapping Input/Output data vector port to AXI4-Stream, Is there any way to enter 32-bit width data while using IP Core Generation workflow?

I would like to know about why we need to convert our data to logical with serializer when we use AXI4-Stream interfaces. I want to use 32-bit width data in/out instantly to my DUT block.

In HDL Coder User Guide, i saw these descriptions below;

"• Connect each DUT input vector data port to a Serializer1D block.

The Serializer1D block must have a ValidOut port and the Ratio set to the vector bit

width.[39-22]"

This situation forces me to use 1-bit flow design in my IP block. So I am getting inefficient design, while i need some speed. Is there any workaround or explanation about this?

Answer 1

[JT Ferrara]

Hi Omer,

There are two modeling styles you can use when mapping to an AXI4-Stream interface:

1. (Sample-based modeling) Model the data signal as a scalar. You must also model the "Valid" control signal in this case. You can optionally model other control signals such as "Ready" and "TLAST".
2. (Frame-based modeling) Model the data signal as a vector. This is intended for HW/SW use cases, where you model the exchange of data between the hardware (FPGA) and software (processor) algorithms. In this case, the software processes frames of data, but the hardware processes streams of data. The serializer inside of your DUT to performs the conversion between frames and samples. The input/output of the DUT are vectors (frames), and the serializer converts the frames to a data and valid signal.

Both cases allow you to model different widths for the data signal. If you are using sample-based modeling approach (#1), then you can set the data type on the scalar "data" signal to the desired bit width, such as "uint32". If you are using frame-based modeling approach (#2), then you can set the data type on the vector "data" signal to the desired bit width, such as "uint32".

More details on the modeling styles can be found here:

https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-stream-interface-generation.html

Hope this helps,

JT