How to generate VHDL code in Xilinx for discrete PID controller for the controller equation is as u(k)=u(k-1)+(28.2671)e(k)+(-55.5204)e(k-1)+(27.2625)e(k-2) ????

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Harshit Derasari am 25 Feb. 2018

the algorithm is Distributed Arithmetic(DA) algorithm based on LUTs(Look up tables)

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How to generate VHDL code in Xilinx for discrete PID controller for the controller equation is as u(k)=u(k-1​)+(28.2671​)e(k)+(-55​.5204)e(k-​1)+(27.262​5)e(k-2) ????