Using Unit Delays in triggered Subsystems for HDL Codegeneration
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Alexander Kiermayer
am 11 Okt. 2017
Beantwortet: Alexander Kiermayer
am 19 Okt. 2017
Hi,
i'm having some Unit Delays in a Triggered Subsystem. When generating VHDL Code using Mathworks HDL Coder I get the following error:
Error: Cannot find valid sample time for clock request from block. Please ensure that the block has a valid discrete sample time.
The only valid value for the sampletime is '-1', which i have set. This error occurs in R2017b, in R2015b it is working.
How can i get this working again?
Best Regards, Alexander Kiermayer
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Tim McBrayer
am 13 Okt. 2017
This should work fine, and does in a small test I just tried. Can you open a customer support case so that this may be further investigated?
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