Referenced model port dimenension issues

I have a project that requires concurrent execution. Because of this I must use referenced models. My project requires frame-based processing and after converting my project from subsystems to referenced models, I’m having worlds of trouble with port dimensions. Specifically, I get error log messages that the input port dimensions are [1x1] (undesired) but this behavior appears to be inconsistent.

Clearly, I need to debug port dimensions. When I compile my project, I get errors against a specific referenced model. Simulink displays port dimension data ONLY for the model that has the first error Simulink detects. I want to backtrack up the project tree to verify dimension data back to the root to solve the problem. However, dimension data is only displayed at the first failing model that Simulink detects. Is there a way to force dimension data to be displayed or deduced for parent models above the first failing model so I can debug where things went wrong?

Also can you give me any insight into the exact backward\forward looking display behavior for port dimensions? Example: I have a model that has three in-ports and they are all frame-based. Simulink displays desired dimension data for one in-port but not the others.

I can’t tell if Simulink is reverse engineering the in-port dimensions based on the destination ports of subordinate blocks or it is correctly deducing the input dimension inheritance. Any clues on how to make this distinction?