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FPGA in loop : verification
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I have some part of my project in VHDL files (quartus) and some part in Matlab hdl coder tool. At this instance I generate code from Matlab and integrate into Quartus project. I would like to know in this situation can I use FPGA in loop verification and how ?
The module in quartus project generates a output which goes into the Matlab generate code and then the output of matalb generated coded again pass the values to the another module in the quartus project as shown in below figure.
I look forward to a reply. Thank you