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Assertion failed: b:\matlab\​src\cgir_h​dl\target_​analysis\c​haracteriz​ationkeyge​nerator.cp​p:45:val

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I am trying to convert a block to HDL using HDL coder with IPcore genration as an option.It throws assertion failed Chareterizationkeygenerator error. Error using hdlcoder.pirctx/doCriticalPathEstimation Assertion failed: b:\matlab\src\cgir_hdl\target_analysis\characterizationkeygenerator.cpp:45:val
Error in slhdlcoder.HDLCoder/makehdl
Error in slhdlcoder.HDLCoder/makehdlturnkey
Error in downstream.DownstreamIntegrationDriver/runIPCoreCodeGen
Error in generateIPCore
Error in Simulink.ModelAdvisor/executeCheckCallbackFct
Error in Simulink.ModelAdvisor/run
Error in Simulink.ModelAdvisor/runCheck
Error in ModelAdvisor.Node/runTaskAdvisor
This is the error list i got .I thought the error might be an issue in Model advisor being outdated and ran it task.mode. But it still throws the same error. Can anyone explain the reason why this error occcurs?
I am usinn arrow Sockit with altera Cyclone v . Thanks in advance

Akzeptierte Antwort

Ram Kokku
Ram Kokku am 30 Jan. 2017
Hi Suneel, thanks for bringing up this issue to our notice. it is a bug. you can work around this problem by turning off CriticalPathEstimation feature. you can do that in many different ways. you can set this off on the model using
hdlset_param(<yourmodelname>, 'CriticalPathEstimation', 'off')
or
from workflow advisor, in HDL Code Generation section, uncheck "Generate high-level timing critical path report".
This change will not affect the quality of the code generated by HDL Coder; however, this will not give you an early report on estimated critical path in your design.
To understand the problem further, I need following information:
1. Model to reproduce the issue
2. Matlab version.
you can send me these details to ram.kokku@mathworks.com
Regards,
Ram

Weitere Antworten (2)

Chinmayi Lanka
Chinmayi Lanka am 20 Jan. 2017
Do you have any Rate Transition blocks in your model? Try removing the Rate Transition blocks from your model and try again. Also, you can try using R2017a_prerelease since the issue does not exist in R2017a_prerelease.
  1 Kommentar
suneel kumar Gaddam
suneel kumar Gaddam am 23 Jan. 2017
I dont have any rate transition blocks it is a single rate all over the model. I think i don't have access to pre release probably because of license issues. Can you suggest further on anything related to Model advisor?

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Kiran Kintali
Kiran Kintali am 7 Mär. 2023
Critical Path Estimation Without Running Synthesis
Critical path is a combinational path between an input and output that has the maximum timing delay. To find the critical path in your design, use HDL Coder™. To make the critical path timing meet the target frequency that you want your design to achieve, break the critical path by adding delays. The additional delays increase the latency and register usage on the target FPGA.
To quickly identify the most likely critical path in your design, use critical path estimation. You then do not have to run synthesis or generate HDL code. Critical path estimation speeds up this iterative process of finding the critical path. It optimizes the critical path until your design timing meets the target frequency that you want.
Generate timing databases for specified target device, device speed grade, and synthesis tool
genhdltdb('Name','Value') generates timing databases for the target device with options specified by using name-value arguments. You can specify the device family name, the device name, the device package, and the device speed grade. This function exports the generated timing database MAT-files to the specified timing database path.
To generate timing databases, the function characterizes basic design components (such as Simulink® blocks, block architectures, and subcomponents of those blocks) for the specified target device. HDL Coder™ analyzes these timing databases to estimate the critical path in your design. For more information, see Critical Path Estimation Without Running Synthesis.

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